Casio QT 6000 Service Manual - Page 95

BR93L46RF IC35, HD74LV00 IC29, logic diagram, each flip-flop positive logic, Pin Name, Function

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3. BR93L46RF (IC35) CS SK DI DO Vcc NC NC GND Pin Name Vcc GND CS SK DI DO I/O Function - Power Supply - GND INPUT Chip Selct INPUT Serial Clock Input INP Start bit,Cord,Address,Serial data OUTPUT Serial data input, READY/BUSY status 4. HD74LV00 (IC29) 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y 5. HD74LV74 (IC25) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X HÜ HÜ H H H H H H L L L H H H L X Q0 Q0 ÜThis configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C D TG TG C C TG Q C C C CLR - 93 -

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— 93 —
3.
BR93L46RF (IC35)
Vcc
NC
NC
GND
CS
SK
DI
DO
Pin Name
I/O
Function
Vcc
-
Power Supply
GND
-
GND
CS
INPUT
Chip Selct
SK
INPUT
Serial Clock Input
DI
INP
Start bit,Cord,Address,Serial data
DO
OUTPUT Serial data input, READY/BUSY status
4.
HD74LV00 (IC29)
1
2
3
4
5
7
6
1A
1B
1Y
2A
2B
GND
2Y
VCC
4B
4A
4Y
3B
3Y
3A
14
13
12
11
10
8
9
5.
HD74LV74 (IC25)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
logic diagram, each flip-flop (positive logic)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
Ü
H
Ü
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
Ü
This configuration is nonstable; that is, it does not
persist when PRE
or CLR returns to its inactive
(high) level.