HP Visualize J5000 hp Visualize J5000, J7000 workstations service handbook (a4 - Page 59

Identifying LCD-Indicated Conditions

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Troubleshooting Identifying LCD-Indicated Conditions Table 3-1. Chassis Codes for J5000 and J7000 Workstations Ostat TST Code 1n26 FRU SYS BD TST 1n27 SYS BD TST 1n28 SYS BD TST 1n29 SYS BD TST 1n2A SYS BD TST 1n2B SYS BD TST 1n2C SYS BD TST 1n30 SYS BD WRN 1n31 SYS BD FLT 1n32 SYS BD INI 1n3C SYS BD TST 1n3E SYS BD TST 1nA0 SYS BD TST 1nA1 SYS BD TST 1nA2 SYS BD TST 1nA3 SYS BD TST 1nA4 SYS BD TST 1nA5 SYS BD TST 1nB1 SYS BD Message CPUn ext intrpt CPUn itimer test CPUn multi-media CPUn shadow reg CPUn diagnse reg CPUn rdr test CPUn bypass test CPUn start est CPUn skip est CPUn bad tst mod CPUn initialize CPUn exit er tst CPUn fpu tests CPUn fpu reg tst CPUn fpu inst CPUn fpu traps CPUn fpu misc CPUn fpu bypass CPUn TLB RAM tst Description CPU n is starting its external interrupt self-test. CPU n is starting its interval timer self-test. CPU n is starting its multi-media instructions self-test. CPU n is starting its shadow register self-test. CPU n is starting its diagnose register self-test. CPU n is starting its remote diagnose register self-test. CPU n is starting its integer bypass operation self-test. CPU n is starting its early (pre-memory) self-tests. CPU n is bypassing its early self-tests to save time. CPU n detected an unsupported system mode. CPU n is initializing after self-tests. CPU n finished its early self-tests. CPU n is starting its floating-point unit self-tests. CPU n is starting its floating-point register self-test. CPU n is starting its floating-point instruction self-test. CPU n is starting its floating-point trap self-test. CPU n is starting its floating-point miscellaneous operations self-test. CPU n is starting its floating-point bypassing self-test. CPU n is starting its TLB register self-test. Chapter 3 55

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Chapter 3
55
Troubleshooting
Identifying LCD-Indicated Conditions
TST
1
n
26
SYS BD
CPU
n
ext intrpt
CPU
n
is starting its external interrupt
self-test.
TST
1
n
27
SYS BD
CPU
n
itimer test
CPU
n
is starting its interval timer
self-test.
TST
1
n
28
SYS BD
CPU
n
multi-media
CPU
n
is starting its multi-media
instructions self-test.
TST
1
n
29
SYS BD
CPU
n
shadow reg
CPU
n
is starting its shadow register
self-test.
TST
1
n
2A
SYS BD
CPU
n
diagnse reg
CPU
n
is starting its diagnose register
self-test.
TST
1
n
2B
SYS BD
CPU
n
rdr test
CPU
n
is starting its remote diagnose
register self-test.
TST
1
n
2C
SYS BD
CPU
n
bypass test
CPU
n
is starting its integer bypass
operation self-test.
TST
1
n
30
SYS BD
CPU
n
start est
CPU
n
is starting its early (pre-memory)
self-tests.
WRN
1
n
31
SYS BD
CPU
n
skip est
CPU
n
is bypassing its early self-tests to
save time.
FLT
1
n
32
SYS BD
CPU
n
bad tst mod
CPU
n
detected an unsupported system
mode.
INI
1
n
3C
SYS BD
CPU
n
initialize
CPU
n
is initializing after self-tests.
TST
1
n
3E
SYS BD
CPU
n
exit er tst
CPU
n
finished its early self-tests.
TST
1
n
A0
SYS BD
CPU
n
fpu tests
CPU
n
is starting its floating-point unit
self-tests.
TST
1
n
A1
SYS BD
CPU
n
fpu reg tst
CPU
n
is starting its floating-point
register self-test.
TST
1
n
A2
SYS BD
CPU
n
fpu inst
CPU
n
is starting its floating-point
instruction self-test.
TST
1
n
A3
SYS BD
CPU
n
fpu traps
CPU
n
is starting its floating-point trap
self-test.
TST
1
n
A4
SYS BD
CPU
n
fpu misc
CPU
n
is starting its floating-point
miscellaneous operations self-test.
TST
1
n
A5
SYS BD
CPU
n
fpu bypass
CPU
n
is starting its floating-point
bypassing self-test.
TST
1
n
B1
SYS BD
CPU
n
TLB RAM tst
CPU
n
is starting its TLB register
self-test.
Table 3-1. Chassis Codes for J5000 and J7000 Workstations
Ostat
Code
FRU
Message
Description