HP Visualize J5000 hp Visualize J5000, J7000 workstations service handbook (a4 - Page 62

Troubleshooting Identifying LCD-Indicated Conditions Table 3-1. Chassis Codes for J5000 and J7000 Workstations Ostat INI FLT Code 3n07 3n09 FRU SYS BD SYS BD WRN 3n1A SYS BD TST 3n1B SYS BD WRN 3n1B SYS BD FLT 3n1B SYS BD TST 3n1C SYS BD WRN 3n1C SYS BD FLT 3n1C SYS BD INI 3n2s SYS BD TST 3nBC IO BD INI 3nBC SYS BD FLT 3nCD IO BD TST 3nCD SYS BD INI 3nCD SYS BD FLT 3nCD SYS BD FLT 3nEC SYS BD FLT 3nF4 SYS BD FLT 3nFC SYS BD TST 4n00 SYS BD Message CPUn invoke LDB bad sys mde byte hversion mismtch chck model strng model str msmtch fatal model str test software ID update sw ID update sw ID err Invoke LDB: s test sys clocks init sys clocks RTC tick timeout check defaults init defaults init EEPROM err bad sys config EEPROM boot limt bad sys bd id CPUn start lst Description CPU n is starting the low-level debugger. CPU n detected an unsupported system mode. Stable store hardware version doesn't match system. Check model string with version in stable store. Model string doesn't match that in stable store. Error reading model string from stable store. Check LANIC address. Update LANIC address. Error updating LANIC address. CPU n is awaiting the low-level debugger for s more seconds. CPU n is verifying processor clocks with the real-time clock. CPU n has initialized the processor clocks. The real time clock is ticking too slowly or not at all. CPU n is initializing stable store values to system defaults. CPU n finished initializing stable store values. CPU n detected an error writing to stable store. CPU n detected an illegal CPU board configuration. CPU n detected a fatal error writing the EEPROM. CPU n cannot identify CPU board. CPU n is starting its late (with memory) self-tests. 58 Chapter 3