HP Visualize J5000 hp Visualize J5000, J7000 workstations service handbook (a4 - Page 63

Ostat, Message, Description

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Troubleshooting Identifying LCD-Indicated Conditions Table 3-1. Chassis Codes for J5000 and J7000 Workstations Ostat WRN Code 4n01 FRU SYS BD TST 4n0E SYS BD TST 4n20 SYS BD TST 4n21 SYS BD TST 4n22 SYS BD TST 4n23 SYS BD TST 4n24 SYS BD TST 4n25 SYS BD TST 4n26 SYS BD TST 4n27 SYS BD TST 4n28 SYS BD TST 4n29 SYS BD TST 4n2A SYS BD TST 4n2B SYS BD TST 4n2C SYS BD TST 4n2D SYS BD TST 4n30 SYS BD TST 4n40 SYS BD TST 4n50 SYS BD Message CPUn skip lst CPUn exit lst CPUn lst erly st CPUn lst basic CPUn lst alu CPUn lst branch CPUn lst arth cd CPUn lst bit ops CPUn lst ctl reg CPUn lst ext int CPUn lst itimer CPUn lst mltimed CPUn lst shadow CPUn lst dg regs CPUn lst rdrs CPUn lst bypass CPUn cache byte CPUn cache flush CPUn icache miss Description CPU n is bypassing its late self-tests to save time. CPU n finished its late self-tests. CPU n is re-executing some of its early self-tests from system memory. CPU n is re-executing its basic operations self-test. CPU n is re-executing its arithmetic and logic unit self-test. CPU n is re-executing its branch instruction self-test. CPU n is re-executing its arithmetic conditions self-test. CPU n is re-executing its bit operations self-test. CPU n is re-executing its control regioster self-test. CPU n is re-executing its external interrupt self-test. CPU n is re-executing its interval timer self-test. CPU n is re-executing its multi-media instructions self-test. CPU n is re-executing its shadow register self-test. CPU n is re-executing its diagnose register self-test. CPU n is re-executing its integer bypass operation self-test. CPU n is starting its data cache sub-word operations self-test. CPU n is starting its cache flush self-test. CPU n is starting its instruction cache miss self-test. Chapter 3 59

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Chapter 3
59
Troubleshooting
Identifying LCD-Indicated Conditions
WRN
4
n
01
SYS BD
CPU
n
skip lst
CPU
n
is bypassing its late self-tests to
save time.
TST
4
n
0E
SYS BD
CPU
n
exit lst
CPU
n
finished its late self-tests.
TST
4
n
20
SYS BD
CPU
n
lst erly st
CPU
n
is re-executing some of its early
self-tests from system memory.
TST
4
n
21
SYS BD
CPU
n
lst basic
CPU
n
is re-executing its basic operations
self-test.
TST
4
n
22
SYS BD
CPU
n
lst alu
CPU
n
is re-executing its arithmetic and
logic unit self-test.
TST
4
n
23
SYS BD
CPU
n
lst branch
CPU
n
is re-executing its branch
instruction self-test.
TST
4
n
24
SYS BD
CPU
n
lst arth cd
CPU
n
is re-executing its arithmetic
conditions self-test.
TST
4
n
25
SYS BD
CPU
n
lst bit ops
CPU
n
is re-executing its bit operations
self-test.
TST
4
n
26
SYS BD
CPU
n
lst ctl reg
CPU
n
is re-executing its control regioster
self-test.
TST
4
n
27
SYS BD
CPU
n
lst ext int
CPU
n
is re-executing its external
interrupt self-test.
TST
4
n
28
SYS BD
CPU
n
lst itimer
CPU
n
is re-executing its interval timer
self-test.
TST
4
n
29
SYS BD
CPU
n
lst mltimed
CPU
n
is re-executing its multi-media
instructions self-test.
TST
4
n
2A
SYS BD
CPU
n
lst shadow
CPU
n
is re-executing its shadow register
self-test.
TST
4
n
2B
SYS BD
CPU
n
lst dg regs
CPU
n
is re-executing its diagnose
register self-test.
TST
4
n
2C
SYS BD
CPU
n
lst rdrs
TST
4
n
2D
SYS BD
CPU
n
lst bypass
CPU
n
is re-executing its integer bypass
operation self-test.
TST
4
n
30
SYS BD
CPU
n
cache byte
CPU
n
is starting its data cache sub-word
operations self-test.
TST
4
n
40
SYS BD
CPU
n
cache flush
CPU
n
is starting its cache flush self-test.
TST
4
n
50
SYS BD
CPU
n
icache miss
CPU
n
is starting its instruction cache
miss self-test.
Table 3-1. Chassis Codes for J5000 and J7000 Workstations
Ostat
Code
FRU
Message
Description