Intel E6600 Specification Update
Intel E6600 - Core 2 Duo Dual-Core Processor Manual
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- Intel E6600 | Specification Update - Page 1
Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update - on 65 nm Process in the 775-land LGA Package supporting Intel® 64Φ Architecture, Intel® Virtualization Technology± and Intel® Trusted Execution Technologyŧ December 2010 - Intel E6600 | Specification Update - Page 2
, Intel SpeedStep, Intel Core, and Core Inside are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop - Intel E6600 | Specification Update - Page 3
Information ...17 Component Identification Information 20 Errata ...23 Specification Changes ...69 Specification Clarifications 70 Documentation Changes ...71 § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 3 Specification Update - Intel E6600 | Specification Update - Page 4
-001 -002 -003 -004 -005 -006 -007 -008 -009 -010 -011 -012 Description • Initial release of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and AI40 • Added Erratum AI58-AI67 • Updated Erratum AI20 - Intel E6600 | Specification Update - Page 5
AI66, AI69, AI72, AI75, AI79, AI91, AI92, AI94, AI101, AI109 • Added processor number E4600 information • Added Erratum AI124 • Updated Plan status for errata AI20, AI24, Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update - Intel E6600 | Specification Update - Page 6
64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 7
associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 - Intel E6600 | Specification Update - Page 8
Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of version of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 9
Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Dual-Core Intel® Xeon® processor LV Dual-Core Intel® Xeon® processor 5100 series Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo - Intel E6600 | Specification Update - Page 10
for Instructions Greater than 15 Bytes May be Preempted AI8 X X X X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts AI9 X X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault 10 Intel® Core™2 Extreme Processor X6800 - Intel E6600 | Specification Update - Page 11
Not Be Flushed by RSM instruction before Restoring the Architectural Supported AI30 X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 12
Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions AI49 X X X X Instruction if it is Followed by an Instruction That Signals a Floating Point Exception 12 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 13
Interrupt is Not Generated when the Current Temperature is Invalid AI66 X X X X Fixed CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address AI70 X X X X Fixed PEBS Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 - Intel E6600 | Specification Update - Page 14
MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 15
Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 16
X X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES - There are no Specification Changes Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence - Intel E6600 | Specification Update - Page 17
2M/800/06 [FPO] e4 ATPO S/N Figure 2. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 - Intel E6600 | Specification Update - Page 18
/1066/06 [FPO] e4 ATPO S/N Figure 4. Intel® Core™2 Duo Desktop Processor 4M SKU Package with 1333 MHz FSB INTEL M ©'05 E6850 INTEL® CORE™2 DUO SLxxx [COO] 3.00GHZ/4M/1333/06 [FPO] e4 ATPO S/N 18 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence - Intel E6600 | Specification Update - Page 19
Identification Information Figure 5. Intel® Core™2 Extreme Processor Package INTEL M ©'05 INTEL® CORE™2 EXTREME 6800 SLxxx [COO] 2.93GHZ/4M/1066/05B [FPO] e4 ATPO S/N § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 19 Specification Update - Intel E6600 | Specification Update - Page 20
The Intel® Core™2 Extreme processor and Intel® Core™2 Duo desktop processor can be identified by the following values: Family1 Model2 0110b 1111b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is - Intel E6600 | Specification Update - Page 21
Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor 9, 10, 11, 12, 13, 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update - Intel E6600 | Specification Update - Page 22
Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 23
the vector will be left set in the in-service register and mask all interrupts at the same or on Single-bit L2 ECC Errors May be Incorrect Problem: When correctable Single-bit ECC errors occur in Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 24
. Implication: The SYSRET instruction can not be used if the RF flag needs to be set after returning from a system call. Intel has not observed this erratum with any commercially available software. 24 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 - Intel E6600 | Specification Update - Page 25
Serviced Before Higher Priority Interrupts Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are normally serviced immediately after the instruction Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 26
APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space threshold value. 26 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence - Intel E6600 | Specification Update - Page 27
Tables of Changes. AI14. LER MSRs May be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and an MWAIT instruction. b) RSM from an SMI during a HLT instruction. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and - Intel E6600 | Specification Update - Page 28
2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked a memory 28 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 29
Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code stream wraps around in a way that one instruction ends FISTTP m32int • FISTTP m64int Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 29 Specification - Intel E6600 | Specification Update - Page 30
Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results Problem: If code sequentially executes off the end of the positive or execution of the instructions found there. 30 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 - Intel E6600 | Specification Update - Page 31
events are to be counted (local core, other core or both cores). Due to this erratum, some Bus Performance Monitoring events may not count when the core-specificity is set to the local core. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 31 - Intel E6600 | Specification Update - Page 32
Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed a #GP fault. 32 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 33
size (64K for 16-bit address size and 4G for 32-bit address size). Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 33 Specification Update - Intel E6600 | Specification Update - Page 34
Incorrect Problem: When a far transfer switches the processor instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code. 34 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 35
(MCE) Problem: When an MCE occurs during execution of a RDMSR instruction for MSRs Actual processor performs a write access to a WB cacheable address within the address range used to perform the MONITOR operation. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 36
in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS (Compare String) and SCAS (Scan String) instructions in 64-bit mode may terminate before the count of Changes. 36 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification - Intel E6600 | Specification Update - Page 37
Memory Image May Be Unexpectedly All 1's after FXSAVE Problem: The upper 32 bits of the FPU Data instruction is executed Implication: Software depending on the full FPU Data (Operand) Pointer may behave unpredictably. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 38
May Disable Non-Bootstrap Processors Problem: When a logical processor encounters an error resulting in shutdown, nonbootstrap processors in the package may be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence - Intel E6600 | Specification Update - Page 39
while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo - Intel E6600 | Specification Update - Page 40
Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction in the IA32 Intel® Architecture Software Developer's Manual, the use of Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and - Intel E6600 | Specification Update - Page 41
Problem: The IO_SMI bit in SMRAM's location 7FA4H is set to "1" by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of executing an instruction Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 - Intel E6600 | Specification Update - Page 42
lost or be corrupted in the presence of STPCLK# assertions. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. 42 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 43
instruction is executed to/from on debug register, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead. Intel® Core™2 Extreme Processor X6800 - Intel E6600 | Specification Update - Page 44
Present to Not Present or from Read/Write to Read Only, etc. • Another processor, without corresponding synchronization and TLB flush, must cause the permission change. 44 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 45
right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Returning back from SMM mode into real mode Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 46
. Implication: When the temperature reaches an invalid temperature the CPU does not generate a VM Exit to Return to a Different Mode Problem: VMLAUNCH/VMRESUME instructions may not fail if the value of the 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 47
AI69. CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address Problem: CPL (Current Privilege Level)-qualified BTS (Branch Trace Store the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 47 Specification - Intel E6600 | Specification Update - Page 48
. Problem: An Asynchronous MCE During a Far Transfer May Corrupt ESP If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. 48 Intel® Core™2 Extreme Processor X6800 and Intel® Core - Intel E6600 | Specification Update - Page 49
Problem: BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts. When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo - Intel E6600 | Specification Update - Page 50
AI79. REP Store Instructions in a Specific Situation may cause the Processor to Hang Problem: During a series of REP (repeat) store instructions a store may Tables of Changes. 50 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification - Intel E6600 | Specification Update - Page 51
SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and - Intel E6600 | Specification Update - Page 52
May Cause the Processor to Hang Problem: When an unaligned access is performed on paging structure entries, accessing a portion of two different entries simultaneously, the processor may live lock. 52 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 - Intel E6600 | Specification Update - Page 53
Fault Problem: If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A bit) may be set for the subsequent page prior to general protection fault on code segment limit. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop - Intel E6600 | Specification Update - Page 54
of shutdown by NMI#. Implication: A processor that has been taken out of shutdown may have an incorrect EFLAGS, CR0 and CR4. In addition the EXF4 signal may still be asserted. 54 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification - Intel E6600 | Specification Update - Page 55
on SYSEXIT and SYSRET Problem: The stack size may instruction is affected. Implication: The count value returned by the performance monitoring event SIMD_UOP_TYPE_EXEC.MUL may be lower than expected. The degree of Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 56
linear address corresponds to the modified PDE o The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that is clear 56 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 57
the Summary Tables of Changes. AI101. Problem: (E)CX May Get Incorrectly Updated When data structures [(E)CX*Data Size] larger than the supported address size structure (64K for 16-bit address Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and - Intel E6600 | Specification Update - Page 58
Count Problem: instruction. The hardware is triggered on subsequent memory store operations to the monitored address range. Due to this erratum, REP STOS/MOVS fast string operations to the monitored address 58 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 59
Machine-Check Exceptions May be Signaled Problem: Executing an instruction stream containing invalid instructions/data may generate a false Level LBR stack is frozen upon Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 59 Specification - Intel E6600 | Specification Update - Page 60
AI108. Problem: VMCALL failure due to corrupt MSEG location may cause VM Exit to load the machine state incorrectly In systems supporting Intel® Tables of Changes. 60 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update - Intel E6600 | Specification Update - Page 61
of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 61 Specification Update - Intel E6600 | Specification Update - Page 62
erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum. 62 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence - Intel E6600 | Specification Update - Page 63
or SFENCE instruction between the string/FXSAVE operation and following store-order sensitive code such as that used for synchronization. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and - Intel E6600 | Specification Update - Page 64
instructions Problem Intel does not support the use of cacheable and WC memory type aliasing, and WC operations are defined as weakly ordered. Status: For the steppings affected, see the Summary Tables of Changes. 64 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor - Intel E6600 | Specification Update - Page 65
Correctly Problem: IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the last update to the IA32_MC1_STATUS MSR. Due to this Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo - Intel E6600 | Specification Update - Page 66
's Manual, Volume 3A, "Exception and Interrupt Reference", if another exception occurs while attempting to call the double-fault handler, the processor enters shutdown mode. However due to this erratum, only 66 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 - Intel E6600 | Specification Update - Page 67
value that was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in the IA32_EFER MSR (C0000080H) at the time of the last SMM VM Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 67 Specification Update - Intel E6600 | Specification Update - Page 68
of Changes. AI129. A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in of Changes. § 68 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification - Intel E6600 | Specification Update - Page 69
Changes listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual volumes 1,2A, 2B, 3A, and 3B All Specification Changes - Intel E6600 | Specification Update - Page 70
listed in this section apply to the following documents: • Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual volumes 1, 2A, 2B, 3A, and 3B All Specification Clarifications - Intel E6600 | Specification Update - Page 71
and IA-32 Architectures Software Developer's manual documentation changes. Follow the link below to become familiar with this file. http://www.intel.com/products/processor/manuals/index.htm § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 71
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Intel
®
Core
™
2 Extreme Processor
X6800
Δ
and Intel
®
Core
™
2 Duo
Desktop Processor E6000
Δ
and
E4000
Δ
Sequence
Specification Update
—
on 65 nm Process in the 775-land LGA Package supporting
Intel
®
64
Φ
Architecture, Intel
®
Virtualization Technology± and
Intel
®
Trusted Execution Technology
ŧ
December 2010
Notice:
The Intel
®
Core
TM
2 Extreme and Intel
®
Core
TM
2 Duo desktop processor may
contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are documented in
this Specification Update.
Document Number:
313279-027