Intel E6600 Specification Update - Page 49

Errata Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown. If the MCE is called with a stack switch, e.g. when the CPL (Current Privilege Level) was changed or when going through an interrupt task gate, then the corrupted ESP will be saved on the stack or in the TSS (Task State Segment), and will not be used. Workaround: Use an interrupt task gate for the machine check handler. Status: For the steppings affected, see the Summary Tables of Changes. AI75. Problem: In Single-Stepping on Branches Mode, the BS Bit in the PendingDebug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM Exit on a MOV to CR8 Instruction In a system supporting Intel® Virtualization Technology, the BS bit (bit 14 of the Pending-Debug-Exceptions field) in the guest state area will be incorrectly set when all of the following conditions occur: • The processor is running in VMX non-root as a 64 bit mode guest; • The "CR8-load existing" VM-execution control is 0 and the "use TPR shadow" VMexecution is 1; • Both BTF (Single-Step On Branches, bit 1) of the IA32_DEBUGCTL MSR (1D9H) Register and the TF (Trap Flag, bit 8) of the RFLAGS Register are set; • "MOV CR8, reg" attempts to program a TPR (Task Priority Register) value that is below the TPR threshold and causes a VM exit. Implication: A Virtual-Machine will sample the BS bit and will incorrectly inject a SingleStep trap to the guest. Workaround: A Virtual-Machine Monitor must manually disregard the BS bit in the Guest State Area in case of a VM exit due to a TPR value below the TPR threshold. Status: For the steppings affected, see the Summary Tables of Changes. AI76. B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following sequence happens: 1) POP instruction to SS (Stack Segment) selector; 2) Next instruction is FP (Floating Point) that gets FP assist followed by code breakpoint. Implication: B0-B3 bits in DR6 may not be properly cleared. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI77. Problem: BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts. When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 49 Specification Update