Intel E6600 Specification Update - Page 62

Errata Status: For the steppings affected, see the Summary Tables of Changes. AI113. Problem: When One Core Executes SEXIT the Other Core's Last Branch Recording May be Incorrect In processors supporting Intel® Trusted Execution Technology when one core is executing SEXIT and the other core is executing a control-transfer instruction, the FROM_IP field contained in the last branch information may be incorrect for the following: • LBR (Last Branch Record) MSRs • BTM (Branch Traces Messages) on the bus • BTS (Branch Trace Store) records written by the debug store mechanism Implication: Due to this erratum, last branch information may be incorrect after one core executes SEXIT. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI114. Problem: A GETSEC[ENTERACCS] Instruction Executed Immediately after GETSEC[WAKEUP] Instruction May Result in a Processor Hang In dual core processor systems supporting Intel® Trusted Execution Technology, a processor hang or unpredictable system behavior may occur if the ILP (Initiating Logical Processor) executes GETSEC[WAKEUP] and then executes GETSEC[ENTERACCS] without making sure that the RLP (Responding Logical Processor) has woken up in between these two instructions. Implication: This may cause the processor to hang or execute code down an unintended path. Workaround: Software must be written to ensure that the RLP has woken-up in response to GETSEC[WAKEUP] instruction and then execute GETSEC[ENTERACCS] instruction. Status: For the steppings affected, see the Summary Tables of Changes. AI115. Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache Problem: A livelock may be observed in rare conditions when instruction fetch causes multiple level one data cache snoops. Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for BIOS to contain a workaround for this erratum. 62 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update