Intel E6600 Specification Update - Page 50

Last Branch Records LBR Updates May be Incorrect After a Task

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Errata instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI78. Last Branch Records (LBR) Updates May be Incorrect After a Task Switch Problem: A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM value to the LBR_TO value. Implication: The LBR_FROM will have the incorrect address of the Branch Instruction. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI79. REP Store Instructions in a Specific Situation may cause the Processor to Hang Problem: During a series of REP (repeat) store instructions a store may try to dispatch to memory prior to the actual completion of the instruction. This behavior depends on the execution order of the instructions, the timing of a speculative jump and the timing of an uncacheable memory store. All types of REP store instructions are affected by this erratum. Implication: When this erratum occurs, the processor may live lock and/or result in a system hang. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI80. Performance Monitoring Events for L1 and L2 Miss May Not be Accurate Problem: Performance monitoring events 0CBh with an event mask value of 02h or 08h (MEM_LOAD_RETIRED.L1_LINE_MISS or MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss events. Implication: Performance monitoring events 0CBh with an event mask value of 02h or 08h may show a count which is lower than expected; the amount by which the count is lower is dependent on other conditions occurring on the same load that missed the cache. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. 50 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

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Errata
50
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
instruction address by the LBR (Last Branch Record) branch-from instruction
address.
Implication:
A BTM/BTS branch-from instruction address may get corrupted for software
interrupts.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI78.
Last Branch Records (LBR) Updates May be Incorrect After a Task
Switch
Problem:
A Task-State Segment (TSS) task switch may incorrectly set the LBR_FROM
value to the LBR_TO value.
Implication:
The LBR_FROM will have the incorrect address of the Branch Instruction.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI79.
REP Store Instructions in a Specific Situation may cause the
Processor to Hang
Problem:
During a series of REP (repeat) store instructions a store may try to dispatch
to memory prior to the actual completion of the instruction.
This behavior
depends on the execution order of the instructions, the timing of a
speculative jump and the timing of an uncacheable memory store.
All types
of REP store instructions are affected by this erratum.
Implication:
When this erratum occurs, the processor may live lock and/or result in a
system hang.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI80.
Performance Monitoring Events for L1 and L2 Miss May Not be
Accurate
Problem:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
(MEM_LOAD_RETIRED.L1_LINE_MISS or
MEM_LOAD_RETIRED.L2_LINE_MISS) may under count the cache miss
events.
Implication:
Performance monitoring events 0CBh with an event mask value of 02h or 08h
may show a count which is lower than expected; the amount by which the
count is lower is dependent on other conditions occurring on the same load
that missed the cache.
Workaround:
None Identified.
Status:
For the steppings affected, see the Summary Tables of Changes.