Intel E6600 Specification Update - Page 68

AI129., A 64-bit Register IP-relative Instruction May Return Unexpected, Results

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Errata exit. If this guideline is followed, that value will be 1 only if the "host address-space size" VM-exit control is 1 in the executive VMCS. Status: For the steppings affected, see the Summary Tables of Changes. AI129. A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP-relative instruction result may be incorrect. Implication: A register IP-relative instruction result may be incorrect and could cause software to read from or write to an incorrect memory location. This may result in an unexpected page fault or unpredictable system behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. § 68 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

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Errata
68
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
exit.
If this guideline is followed, that value will be 1 only if the “host
address-space size” VM-exit control is 1 in the executive VMCS.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI129.
A 64-bit Register IP-relative Instruction May Return Unexpected
Results
Problem:
Under an unlikely and complex sequence of conditions in 64-bit mode, a
register IP-relative instruction
result may be incorrect.
Implication:
A register IP-relative instruction result may be incorrect and could cause
software to read from or write to an incorrect memory location. This may
result in an unexpected page fault or unpredictable system behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
§