Intel E6600 Specification Update - Page 51

Errata AI81. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Problem: When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. Implication: Software that uses WB to WT memory aliasing may violate proper store ordering. Workaround: Do not use WB to WT aliasing. Status: For the steppings affected, see the Summary Tables of Changes. AI82. A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified Problem: Moves to/from control registers are supposed to ignore REW.W and the 66H (operand size) prefix. In systems supporting Intel® Virtualization Technology, when the processor is operating in VMX non-root operation and "use TPR shadow" VM-execution control is set to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of storing zeros in them. Implication: Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI83. Non-Temporal Data Store May be Observed in Wrong Program Order Problem: When non-temporal data is accessed by multiple read operations in one thread while another thread performs a cacheable write operation to the same address, the data stored may be observed in wrong program order (i.e. later load operations may read older data). Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may observe data in wrong program order. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Write Combining Memory Locations" will operate correctly. Status: For the steppings affected, see the Summary Tables of Changes. AI84. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track retired SSE instructions. Due to this erratum, the processor may Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 51 Specification Update