Intel E6600 Specification Update - Page 14

Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI74 X X X X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP AI75 X X X X Fixed In Single-Stepping on Branches Mode, the BS Bit in the Pending-Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction AI76 X X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint AI77 X X X X X No Fix BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts AI78 X X X X X No Fix Last Branch Records (LBR) Updates May be Incorrect After a Task Switch AI79 X X X X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads AI82 X X X X X No Fix A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Register Unmodified AI83 X X X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program Order AI84 X X X X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values AI85 X X X X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame AI86 X X Fixed CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available AI87 X X X X X No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang AI88 X X X X X No Fix Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior AI89 X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AI90 X X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault AI91 X X X X Fixed Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior AI92 X X X X Fixed Invalid Instructions May Lead to Unexpected Behavior AI93 X X X X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown AI94 X X X X Fixed Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update