Intel E6600 Specification Update - Page 33

EIP May be Incorrect after Shutdown in IA-32e Mode

Get Intel E6600 - Core 2 Duo Dual-Core Processor PDF manuals and user guides
UPC - 735858184625
View all Intel E6600 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 33 highlights

Errata Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4G limit (0ffffffffh). Status: For the steppings affected, see the Summary Tables of Changes. AI28. EIP May be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown state the upper 32 bits of the instruction pointer may be incorrect. This may be observed if the processor is taken out of shutdown state by NMI#. Implication: A processor that has been taken out of the shutdown state may have an incorrect EIP. The only software which would be affected is diagnostic software that relies on a valid EIP. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI29. #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit is Not Supported Problem: A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a processor which does not support Execute Disable Bit functionality. Implication: Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating a fault. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI30. (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Problem: When performing Fast String REP MOVS or REP STOS commands with data structures [(E)CX*Data Size] larger than the supported address size structure (64K for 16-bit address size and 4G for 32-bit address size) some addresses may be processed more than once. After an amount of data greater than or equal to the address size structure has been processed, external events (such as interrupts) will cause the (E)CX registers to be increment by a value that corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit address size. Implication: (E)CX may contain an incorrect count which may cause some of the MOVS or STOS operations to re-execute. Intel has not observed this erratum with any commercially available software. Workaround: Do not use values in (E)CX that when multiplied by the data size give values larger than the address space size (64K for 16-bit address size and 4G for 32-bit address size). Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 33 Specification Update

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
Errata
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
33
Specification Update
Workaround:
Software should ensure that memory accesses in 32-bit mode do not occur
above the 4G limit (0ffffffffh).
Status:
For the steppings affected, see the Summary Tables of Changes.
AI28.
EIP May be Incorrect after Shutdown in IA-32e Mode
Problem:
When the processor is going into shutdown state the upper 32 bits of the
instruction pointer may be incorrect. This may be observed if the processor is
taken out of shutdown state by NMI#.
Implication:
A processor that has been taken out of the shutdown state may have an
incorrect EIP. The only software which would be affected is diagnostic
software that relies on a valid EIP.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI29.
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Bit is Not Supported
Problem:
A #GP fault is not generated on writing to IA32_MISC_ENABLE [34] bit in a
processor which does not support Execute Disable Bit functionality.
Implication:
Writing to IA32_MISC_ENABLE [34] bit is silently ignored without generating
a fault.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI30.
(E)CX May Get Incorrectly Updated When Performing Fast String REP
MOVS or Fast String REP STOS With Large Data Structures
Problem:
When performing Fast String REP MOVS or REP STOS commands with data
structures [(E)CX*Data Size] larger than the supported address size structure
(64K for 16-bit address size and 4G for 32-bit address size) some addresses
may be processed more than once. After an amount of data greater than or
equal to the address size structure has been processed, external events (such
as interrupts) will cause the (E)CX registers to be increment by a value that
corresponds to 64K bytes for 16 bit address size and 4G bytes for 32 bit
address size.
Implication:
(E)CX may contain an incorrect count which may cause some of the MOVS or
STOS operations to re-execute. Intel has not observed this erratum with any
commercially available software.
Workaround:
Do not use values in (E)CX that when multiplied by the data size give values
larger than the address space size (64K for 16-bit address size and 4G for
32-bit address size).
Status:
For the steppings affected, see the Summary Tables of Changes.