Intel E6600 Specification Update - Page 34

Errata AI31. Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate Problem: The following events may be counted as instructions that contain a load by the MEM_LOAD_RETIRED performance monitor events and may be counted as loads by the INST_RETIRED (mask 01H) performance monitor event: • Prefetch instructions • x87 exceptions on FST* and FBSTP instructions • Breakpoint matches on loads, stores, and I/O instructions • Stores which update the A and D bits • Stores that split across a cache line • VMX transitions • Any instruction fetch that misses in the ITLB Implication: The MEM_LOAD_RETIRED and INST_RETIRED (mask 01H) performance monitor events may count a value higher than expected. The extent to which the values are higher than expected is determined by the frequency of the above events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI32. Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect Problem: When a far transfer switches the processor from 32-bit mode to IA-32e mode, the upper 32 bits of the 'From' (source) addresses reported through the BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect. Implication: The upper 32 bits of the 'From' address debug information reported through BTMs or BTSs may be incorrect during this transition Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI33. Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results Problem: The act of one processor, or system bus master, writing data into a currently executing code segment of a second processor with the intent of having the second processor execute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to execute a synchronizing instruction, prior to execution of the new code, is called unsynchronized XMC. Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unexpected or unpredictable execution behavior from the processor that is executing the modified code. 34 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update