Intel E6600 Specification Update - Page 16

Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations VM Exit with Exit Reason "TPR Below Threshold" Can Cause the AI118 X X X X X No Fix Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field AI119 X X X X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types May Lead to Memory Ordering Violations AI120 X X X X X No Fix VM Exit due to Virtual APIC-Access May Clear RF AI121 Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the Processor is Reset AI122 X Fixed VTPR Access May Lead to System Hang AI123 X Fixed IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly AI124 X X X X X No Fix RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results AI125 X X X Fixed NMIs May Not Be Blocked by a VM-Entry Failure AI126 X X X X X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown AI127 X X X X X No Fix A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS AI128 X X X X X No Fix A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort When Expected AI129 X X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES - There are no Specification Changes in this Specification Update revision. Number SPECIFICATION CLARIFICATIONS AI1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Number DOCUMENTATION CHANGES - There are no Documentation Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update