Intel E6600 Specification Update - Page 38

Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM - cpu

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Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI43. Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior Problem: When a logical processor writes to a non-dirty page, and another logicalprocessor either writes to the same non-dirty page or explicitly sets the dirty bit in the corresponding page table entry, complex interaction with internal processor activity may cause unpredictable system behavior. Implication: This erratum may result in unpredictable system behavior and hang. Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI44. Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate Problem: Performance monitoring events that count the number of cycles the divider is busy and no other execution unit operation or load operation is in progress may not be accurate. Implication: The counter may reflect a value higher or lower than the actual number of events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI45. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. Note: This issue would only occur when one of the 3 above mentioned debug support facilities are used. Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI46. Shutdown Condition May Disable Non-Bootstrap Processors Problem: When a logical processor encounters an error resulting in shutdown, nonbootstrap processors in the package may be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

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Errata
38
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI43.
Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
Problem:
When a logical processor writes to a non-dirty page, and another logical-
processor either writes to the same non-dirty page or explicitly sets the dirty
bit in the corresponding page table entry, complex interaction with internal
processor activity may cause unpredictable system behavior.
Implication:
This erratum may result in unpredictable system behavior and hang.
Workaround:
It is possible for BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI44.
Performance Monitor IDLE_DURING_DIV (18h) Count May Not be
Accurate
Problem:
Performance monitoring events that count the number of cycles the divider is
busy and no other execution unit operation or load operation is in progress
may not be accurate.
Implication:
The counter may reflect a value higher or lower than the actual number of
events.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI45.
Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem:
After a return from SMM (System Management Mode), the CPU will
incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace
Store), hence rendering their data invalid. The corresponding data if sent out
as a BTM on the system bus will also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.
Implication:
The value of the LBR, BTS, and BTM immediately after an RSM operation
should not be used.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI46.
Shutdown Condition May Disable Non-Bootstrap Processors
Problem:
When a logical processor encounters an error resulting in shutdown, non-
bootstrap processors in the package may be unexpectedly disabled.