Intel E6600 Specification Update - Page 60

VT APIC Access in a Guest with the DS Save, Area May Lead to Unpredictable Behavior

Get Intel E6600 - Core 2 Duo Dual-Core Processor PDF manuals and user guides
UPC - 735858184625
View all Intel E6600 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 60 highlights

Errata the occurrence of a hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e. before the hardware PMI request). Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR information that does not describe the last few branches before the PEBS sample that triggered the PMI. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI108. Problem: VMCALL failure due to corrupt MSEG location may cause VM Exit to load the machine state incorrectly In systems supporting Intel® Virtualization Technology, if a VMCALL failure occurs due to a corrupt Monitor Segment (MSEG), subsequent VM Exits may load machine state incorrectly. Implication: Occurrence of this erratum may result in a VMX abort. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI109. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of a branch record or a PEBS (precise-event-based-sampling) record to the DS (debug store) save area that overlaps with the APIC access page may lead to unpredictable behavior. Implication: Guest software configured to log branch records or PEBS records cannot specify the DS (debug store) save area within the APIC-access page. Under any expected usage model this type of overlap is not expected to exist. One should be aware of the fact that the specified DS address is of linear form while the APIC access page is of a physical form. Any solution that wishes to avoid this condition will need to comprehend the linear-to-physical translation of the DS related address pointers with respect to the mapping of the physical APIC access page to avoid such an overlap. Under normal circumstances for correctly written software, such an overlap is not expected to exist. Intel has not observed this erratum with any commercially available software. Workaround: For a fully comprehensive workaround, the VMM should not allow the logging of branch or PEBS records while guest software is running if the "virtualize APIC accesses" VM-execution control is 1. Status: For the steppings affected, see the Summary Tables of Changes. 60 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
Errata
60
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
the occurrence of a hardware PMI request. Due to this erratum, the LBR
freeze may occur too soon (i.e. before the hardware PMI request).
Implication:
Following a PMI occurrence, the PMI handler may observe old/out-of-date
LBR information that does not describe the last few branches before the PEBS
sample that triggered the PMI.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI108.
VMCALL failure due to corrupt MSEG location may cause VM Exit to
load the machine state incorrectly
Problem:
In systems supporting Intel
®
Virtualization Technology, if a VMCALL failure
occurs due to a corrupt Monitor Segment (MSEG), subsequent VM Exits may
load machine state incorrectly.
Implication:
Occurrence of this erratum may result in a VMX abort.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI109.
Overlap of an Intel
®
VT APIC Access Page in a Guest with the DS Save
Area May Lead to Unpredictable Behavior
Problem:
Logging of a branch record or a PEBS (precise-event-based-sampling) record
to the DS (debug store) save area that overlaps with the APIC access page
may lead to unpredictable behavior.
Implication:
Guest software configured to log branch records or PEBS records
cannot specify the DS (debug store) save area within the APIC-access page.
Under any expected usage model this type of overlap is not expected to exist.
One should be aware of the fact that the specified DS address is of linear
form while the APIC access page is of a physical form. Any solution that
wishes to avoid this condition will need to comprehend the linear-to-physical
translation of the DS related address pointers with respect to the mapping of
the physical APIC access page to avoid such an overlap. Under normal
circumstances for correctly written software, such an overlap is not expected
to exist. Intel has not observed this erratum with any commercially available
software.
Workaround:
For a fully comprehensive workaround, the VMM should not allow the logging
of branch or PEBS records while guest software is running if the "virtualize
APIC accesses" VM-execution control is 1.
Status:
For the steppings affected, see the Summary Tables of Changes.