Intel E6600 Specification Update - Page 56

Errata undercount depends on actual occurrences of PMULUDQ instructions, while the counter is active. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI97. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow. Due to this erratum, if the counter overflow occurs after execution of either MOV SS or STI, storage of the PEBS record is delayed by one instruction. Implication: When this erratum occurs, software may observe storage of the PEBS record being delayed by one instruction following execution of MOV SS or STI. The state information in the PEBS record will also reflect the one instruction delay. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI98. Problem: Store Ordering May be Incorrect between WC and WP Memory Types According to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A "Methods of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to this erratum, WP stores may not drain the WC buffers. Implication: Memory ordering may be violated between WC and WP stores. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI99. Problem: Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #PF Code #PF (Page Fault exception) is normally handled in lower priority order relative to both code #DB (Debug Exception) and code Segment Limit Violation #GP (General Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of the following conditions are met: • A PDE (Page Directory Entry) is modified without invalidating the corresponding TLB (Translation Look-aside Buffer) entry • Code execution transitions to a different code page such that both o The target linear address corresponds to the modified PDE o The PTE (Page Table Entry) for the target linear address has an A (Accessed) bit that is clear 56 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update