Intel E6600 Specification Update - Page 66

Benign Exception after a Double Fault May Not Cause a Triple Fault

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Errata erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit. Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AI124. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results. Implication: In the above sequence, the processor may live lock or hang, or RSM instruction may restart the interrupted processor context through a nondeterministic EIP offset in the code segment, resulting in unexpected instruction execution, unexpected exceptions or system hang. Intel has not observed this erratum with any commercially available software. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AI125. Problem: NMIs May Not Be Blocked by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 specifies that, following a VM-entry failure during or after loading guest state, "the state of blocking by NMI is what it was before VM entry." If non-maskable interrupts (NMIs) are blocked and the "virtual NMIs" VM-execution control set to 1, this erratum may result in NMIs not being blocked after a VM-entry failure during or after loading guest state. Implication: VM-entry failures that cause NMIs to become unblocked may cause the processor to deliver an NMI to software that is not prepared for it. Workaround: VMM software should configure the virtual-machine control structure (VMCS) so that VM-entry failures do not occur. Status: For the steppings affected, see the Summary Tables of Changes. AI126. Problem: Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown According to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, "Exception and Interrupt Reference", if another exception occurs while attempting to call the double-fault handler, the processor enters shutdown mode. However due to this erratum, only 66 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update

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Errata
66
Intel
®
Core™2 Extreme Processor X6800 and
Intel
®
Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of
the IA32_MC1_CTL MSR enable bit.
Implication:
IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the
enable bit in the IA32_MC1_CTL MSR at the time of the last update.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI124.
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
Problem:
RSM instruction execution, under certain conditions triggered by a complex
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication:
In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
instruction execution, unexpected exceptions or system hang.
Intel has not
observed this erratum with any commercially available software.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI125.
NMIs May Not Be Blocked by a VM-Entry Failure
Problem:
The
Intel
®
64 and IA-32 Architectures Software Developer’s Manual Volume
3B: System Programming Guide,
Part 2 specifies that, following a VM-entry
failure during or after loading guest state, “the state of blocking by NMI is
what it was before VM entry.” If non-maskable interrupts (NMIs) are blocked
and the “virtual NMIs” VM-execution control set to 1, this erratum may result
in NMIs not being blocked after a VM-entry failure during or after loading
guest state.
Implication:
VM-entry failures that cause NMIs to become unblocked may cause the
processor to deliver an NMI to software that is not prepared for it.
Workaround:
VMM software should configure the virtual-machine control structure (VMCS)
so that VM-entry failures do not occur.
Status:
For the steppings affected, see the Summary Tables of Changes.
AI126.
Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown
Problem:
According to the
Intel
®
64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A
, “Exception and Interrupt Reference”, if another
exception occurs while attempting to call the double-fault handler, the
processor enters shutdown mode.
However due to this erratum, only