Intel Q9400S Data Sheet

Intel Q9400S - Core 2 Quad 2.66GHz 6M L2 Cache 1333MHz LGA775 Low Power Processor Manual

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  • Intel Q9400S | Data Sheet - Page 1
    Intel® Core™2 Extreme Processor QX9000Δ Series, Intel® Core™2 Quad Processor Q9000Δ, Q9000SΔ, Q8000Δ, and Q8000SΔ Series Datasheet - on 45 nm process in the 775 land package August 2009 Document Number: 318726-010
  • Intel Q9400S | Data Sheet - Page 2
    property rights. The Intel® Core™2 Extreme processor QX9000 series and Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata
  • Intel Q9400S | Data Sheet - Page 3
    Contents 1 Introduction ...11 1.1 Terminology ...12 1.1.1 Processor Terminology Definitions 12 1.2 References ...14 2 Electrical Specifications 15 2.1 Power and Ground Lands 15 2.2 Decoupling Guidelines 15 2.2.1 VCC Decoupling 15 2.2.2 Vtt Decoupling 15 2.2.3 FSB Decoupling 16 2.3 Voltage
  • Intel Q9400S | Data Sheet - Page 4
    Requirements 97 7.3.1 Fan Heatsink Power Supply 97 7.4 Thermal Specifications 99 7.4.1 Boxed Processor Cooling Requirements 99 7.4.2 Variable Speed Fan 100 7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications 101 7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight
  • Intel Q9400S | Data Sheet - Page 5
    Profile 80 5-4 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-5 Case Temperature (TC) Measurement Location 82 5-6 Thermal Monitor 2 Frequency and Voltage Ordering 84 5-7 Conceptual Fan Control Diagram on PECI-Based Platforms 86 6-1 Processor Low Power State Machine
  • Intel Q9400S | Data Sheet - Page 6
    5-4 Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 5-5 Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5-6 GetTemp0() Error Codes 87 6-1 Power-On Configuration Option Signals 89 7-1 Fan Heatsink Power and Signal Specifications 98 7-2 Fan Heatsink
  • Intel Q9400S | Data Sheet - Page 7
    Core™2 Quad processor Q8200 • Added Intel® Core™2 Quad processor Q8300 • Added Intel® Core™2 Quad processor Q9000S and Q8000S series - Q9550S, Q9400S, and Q8200S. • Added Intel® Core™2 Quad processors Q8400 and Q8400S • Corrected list of Intel® VT supported processors: Intel® Core™2 Quad processors
  • Intel Q9400S | Data Sheet - Page 8
    8 Datasheet
  • Intel Q9400S | Data Sheet - Page 9
    to take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep® technology, allows tradeoffs to be made between performance and power consumption. The Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S
  • Intel Q9400S | Data Sheet - Page 10
    Intel Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology. Virtualization Technology provides silicon-based functionality that works together with compatible Virtual
  • Intel Q9400S | Data Sheet - Page 11
    , the Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000 and Q9000S series, and Intel® Core™2 Quad processors Q8400 and Q8400S support Intel® Virtualization Technology (Intel® VT). Further, the Intel® Core™2 Quad processor Q9000 and Q9000S series support Intel® Trusted
  • Intel Q9400S | Data Sheet - Page 12
    MB L2 caches or two 2 MB L2 caches.. • Intel® Core™2 Quad processor Q9000S series - Low power Quad core processor in the FC-LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches. • Intel® Core™2 Quad Processor Q8000S Series - Low power Quad core processor in the FC-LGA8 package with two 4 MB L2
  • Intel Q9400S | Data Sheet - Page 13
    trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). • Intel® Virtualization Technology (Intel® VT) - A set of hardware enhancements to Intel server and client platforms that can
  • Intel Q9400S | Data Sheet - Page 14
    11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket Balanced Technology Extended (BTX) System Design Guide LGA775 Socket Mechanical Design Guide Intel® 64 and IA-32 Intel Architecture Software Developer's Manuals Volume 1: Basic Architecture Volume 2A: Instruction Set Reference
  • Intel Q9400S | Data Sheet - Page 15
    Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with
  • Intel Q9400S | Data Sheet - Page 16
    ® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, and Q8000S Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power
  • Intel Q9400S | Data Sheet - Page 17
    Electrical Specifications Table 2-1. Voltage Identification Definition VID VID VID VID VID VID VID VID 76543210 Voltage 00000000 OFF 00000010 1.6 0 0 0 0 0 1 0 0 1.5875 0 0 0 0 0 1 1 0 1.575 0 0 0 0 1 0 0 0 1.5625 00001010 1.55 0 0 0 0 1 1 0 0 1.5375 0 0 0 0 1 1 1 0 1.525 0 0 0 1 0 0
  • Intel Q9400S | Data Sheet - Page 18
    for designs supporting boundary scan for proper Boundary Scan testing of the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130 W TDP processor installed in a board with a 65 W or 95 W TDP capable VR may draw too much power
  • Intel Q9400S | Data Sheet - Page 19
    Core voltage with respect to VSS -0.3 VTT FSB termination voltage with respect to VSS -0.3 TCASE Processor case temperature See Section 5 TSTORAGE Processor storage temperature refer to the processor case temperature specifications. 4. This rating applies to the processor and does not
  • Intel Q9400S | Data Sheet - Page 20
    2.6.2 DC Voltage and Current Specification Table 2-3. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes2, 10 VID Range VCC Core VCC_BOOT VCCPLL VID 0.8500 - 1.3625 V Processor Number V QX9770 3.20 GHz (12 MB Cache) Processor Number VCC for 775_VR_CONFIG_05B
  • Intel Q9400S | Data Sheet - Page 21
    VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT ICC_VCCPLL ICC_GTLREF QX9770 Processor Number QX9650 Processor Number Q9650 Q9550 Q9550S Q9505 Q9505S Q9450 Q9400 Q9400S Q9300 Q8400 Q8300 Q8200 Q8400S Q8200S FSB termination voltage (DC + AC specifications) 3.20 GHz (12 MB Cache) ICC for 775_VR_CONFIG_05B
  • Intel Q9400S | Data Sheet - Page 22
    line. Refer to the Voltage Regulator Design Guide to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. 10. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 22 Datasheet
  • Intel Q9400S | Data Sheet - Page 23
    for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation. Datasheet 23
  • Intel Q9400S | Data Sheet - Page 24
    except for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR
  • Intel Q9400S | Data Sheet - Page 25
    NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. Die Voltage Validation Overshoot events on processor must meet the specifications in Table 2-5 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be
  • Intel Q9400S | Data Sheet - Page 26
    defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies motherboard (see Table 2-13 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
  • Intel Q9400S | Data Sheet - Page 27
    Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals1 GTL+ Strobes CMOS Open Drain Output Open Drain Input/Output FSB Clock Power . 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port
  • Intel Q9400S | Data Sheet - Page 28
    timing requirements for entering and leaving the low power states. 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise
  • Intel Q9400S | Data Sheet - Page 29
    of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification. Datasheet 29
  • Intel Q9400S | Data Sheet - Page 30
    VTT min/max specifications. Refer to Table 2-3 for VTT specifications. 2. The leakage specification applies to powered devices on 4 25.15 Ω 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a
  • Intel Q9400S | Data Sheet - Page 31
    2-14 for the processor supported ratios). The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB
  • Intel Q9400S | Data Sheet - Page 32
    must operate at the same frequency. The Intel® Core™2 Extreme processor QX9650, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series operate at a 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). The Intel® Core™2 Extreme processor QX9770 operates at a 1600 MHz FSB
  • Intel Q9400S | Data Sheet - Page 33
    [1:0] Rise and Fall Slew Rate 2.5 - 8 V/ns 2-4 4 Slew Rate Matching N/A N/A 20 % - 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK[1:0]. 2. The period specified here is the average period. A given
  • Intel Q9400S | Data Sheet - Page 34
    Electrical Specifications . Figure 2-3. Differential Clock Waveform Threshold Region Tph BCLK1 VCROSS (ABS) VCROSS (ABS) Ringback Margin BCLK0 Tpl Tp Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (
  • Intel Q9400S | Data Sheet - Page 35
    Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated
  • Intel Q9400S | Data Sheet - Page 36
    Figure 3-2. Processor Package Drawing (Sheet 1 of 3) Package Mechanical Specifications 36 Datasheet
  • Intel Q9400S | Data Sheet - Page 37
    Package Mechanical Specifications Figure 3-3. Processor Package Drawing (Sheet 2 of 3) Datasheet 37
  • Intel Q9400S | Data Sheet - Page 38
    Figure 3-4. Processor Package Drawing (Sheet 3 of 3) Package Mechanical Specifications 38 Datasheet
  • Intel Q9400S | Data Sheet - Page 39
    clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms
  • Intel Q9400S | Data Sheet - Page 40
    can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the
  • Intel Q9400S | Data Sheet - Page 41
    Package Mechanical Specifications Figure 3-6. Processor Top-Side Markings Example (Intel® Core™2 Quad Processor Q9000 Series) INTEL M ©'06 Q9550 INTEL® CORE™2 Quad SLAN3 XXXX 2.83GHZ/2M/1333/05A [FPO](ee4 4) ATPO S/N Datasheet 41
  • Intel Q9400S | Data Sheet - Page 42
    Package Mechanical Specifications . Figure 3-7. Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants, Top View V CC / V SS 30 29 28 27 26 25 24 23 22 21 20
  • Intel Q9400S | Data Sheet - Page 43
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 4-1 and Figure 4-2. These
  • Intel Q9400S | Data Sheet - Page 44
    Land Listing and Signal Descriptions Figure 4-1.land-out Diagram (Top View - Left Side) 30 29 28 AN VCC VCC VSS AM VCC VCC VSS AL VCC VCC VSS AK VSS VSS VSS AJ VSS VSS VSS AH VCC VCC VCC AG VCC VCC VCC AF VSS VSS VSS AE VSS VSS VSS AD VCC VCC VCC AC VCC VCC VCC AB VSS VSS VSS AA VSS VSS
  • Intel Q9400S | Data Sheet - Page 45
    Land Listing and Signal Descriptions Figure 4-2.land-out Diagram (Top View - Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS
  • Intel Q9400S | Data Sheet - Page 46
    Common Clock Input Common Clock Input/Output Asynch CMOS Output Asynch CMOS Output Asynch CMOS Output Power/Other Input Power/Other Input Power/Other Input Power/Other Input Power/Other Input Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source
  • Intel Q9400S | Data Sheet - Page 47
    Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other FC31 FC32 J16 H15 Power/Other Power/Other FC33 FC34 H16 J17 Power/Other Power/Other FC35 FC36
  • Intel Q9400S | Data Sheet - Page 48
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel Q9400S | Data Sheet - Page 49
    AG19 AG21 AG22 AG25 AG26 AG27 AG28 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VCC VCC AG29 AG30 Power/Other Power/Other VCC VCC AG8 AG9 Power/Other Power/Other VCC VCC AH11 AH12
  • Intel Q9400S | Data Sheet - Page 50
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel Q9400S | Data Sheet - Page 51
    AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Output Output Output Output
  • Intel Q9400S | Data Sheet - Page 52
    AL10 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel Q9400S | Data Sheet - Page 53
    VSS H26 H27 H28 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Table 4-1. Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS
  • Intel Q9400S | Data Sheet - Page 54
    D28 D29 D30 J1 AA1 F27 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output Output 54
  • Intel Q9400S | Data Sheet - Page 55
    VSS VSS VSS VSS VSS VSS VSS IERR# FC37 Power/Other Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch CMOS Power/Other Input/Output Input/Output Output AB4 AB5 A26# A24
  • Intel Q9400S | Data Sheet - Page 56
    Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
  • Intel Q9400S | Data Sheet - Page 57
    VSS VCC VCC VSS VSS VCC VCC VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AK29 AK30 VSS VSS Power/Other Power/Other AL1 FC25 Power/Other AL2 PROCHOT# Asynch CMOS Input/Output
  • Intel Q9400S | Data Sheet - Page 58
    FC23 VTT VTT VTT VTT VTT VTT VSS D10# VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input Source Synch Input/Output Source Synch
  • Intel Q9400S | Data Sheet - Page 59
    VSS VTT VTT VTT VTT VTT VTT RESERVED ADS# Source Synch Source Synch Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input/Output Common Clock Input/Output D3 VSS Power/Other D4 HIT# Common Clock Input/Output D5 VSS
  • Intel Q9400S | Data Sheet - Page 60
    /Other Input Power/Other Input Power/Other Input Power/Other Input Clock Input Asynch CMOS Output Asynch CMOS Output Power/Other Input Power/Other Input Power/Other Power/Other Power/Other Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 60
  • Intel Q9400S | Data Sheet - Page 61
    VSS VSS VSS Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other H25 H26 VSS VSS Power/Other Power/Other H27 H28 VSS VSS Power/Other Power/Other H29 H30 FC15 BSEL1 Power/Other Asynch CMOS
  • Intel Q9400S | Data Sheet - Page 62
    /Other Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Output Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output
  • Intel Q9400S | Data Sheet - Page 63
    Direction V7 VSS Power/Other V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other V27 VSS Power/Other V28 VSS Power/Other V29 VSS Power/Other V30 VSS Power/Other W1 MSID0 Power/Other W2 TDI_M Power/Other W3 TESTHI1
  • Intel Q9400S | Data Sheet - Page 64
    processor samples a subset of the A[35:3]# signals to determine power- processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction
  • Intel Q9400S | Data Sheet - Page 65
    processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[3:0]# are associated with core 0. BPMb[3:0]# are associated with core system and is used by the processor to request the bus. During power-on configuration this signal is sampled
  • Intel Q9400S | Data Sheet - Page 66
    data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common D[31:16]# DBI0# D[15:0]# DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by
  • Intel Q9400S | Data Sheet - Page 67
    power state, requires chipset support and may not be available on all platforms. NOTE: Some processors may not have the Deep Sleep State enabled, refer to the Specification Update for specific by the processor. When this land is tied to VSS, previous processors based on the Intel NetBurst®
  • Intel Q9400S | Data Sheet - Page 68
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. GTLREF[3:0] determine the signal
  • Intel Q9400S | Data Sheet - Page 69
    are not connected on the package (they are floating). As an alternative to MSID, Intel has implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor. Refer to Section 2.5 for additional information regarding PSID. PECI is a proprietary one-wire bus
  • Intel Q9400S | Data Sheet - Page 70
    Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications /lands of all processor FSB agents. SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers
  • Intel Q9400S | Data Sheet - Page 71
    to core 1. TDO and TDO_M (Test Data Out) transfers serial test data out of the processor. TDO and TDO_M provide the serial output needed for JTAG specification support. TDO connects to core 1. TDO_M connects to core 0. TESTHI[10,7:0] must be connected to the processor's appropriate power source
  • Intel Q9400S | Data Sheet - Page 72
    will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD (provided VTT and VCC are valid). TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY
  • Intel Q9400S | Data Sheet - Page 73
    support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator Design Guide for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor are needed to support the processor voltage specification variations. See
  • Intel Q9400S | Data Sheet - Page 74
    Land Listing and Signal Descriptions 74 Datasheet
  • Intel Q9400S | Data Sheet - Page 75
    In order to determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer
  • Intel Q9400S | Data Sheet - Page 76
    are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor feature is
  • Intel Q9400S | Data Sheet - Page 77
    Thermal Specifications and Design Considerations Table 5-2. Intel® Core™2 Extreme Processor QX9770 Thermal Profile Power Maximum (W) Tc (°C) 0 37.8 2 38.1 4 38.3 6 38.6 8 38.8 10 39.1 12 39.4 14 39.6 16 39.9 18 40.1 20 40.4 22 40.7 24 40.9 26 41.2
  • Intel Q9400S | Data Sheet - Page 78
    Thermal Specifications and Design Considerations Table 5-3. Intel® Core™2 Extreme Processor QX9650 Thermal Profile Power Maximum (W) Tc (°C) 0 42.4 2 42.7 4 43.1 6 43.4 8 43.8 10 44.1 12 44.4 14 44.8 16 45.1 18 45.5 20 45.8 22 46.1 24 46.5 26 46.8
  • Intel Q9400S | Data Sheet - Page 79
    Thermal Specifications and Design Considerations Table 5-4. Intel® Core™2 Quad Processor Q9000 and Q8000 Series Thermal Profile Power Maximum (W) Tc (°C) 0 44.8 2 45.4 4 45.9 6 46.5 8 47.0 10 47.6 12 48.2 14 48.7 16 49.3 18 49.8 20 50.4 22 51.0 24 51.5 Power Maximum (W)
  • Intel Q9400S | Data Sheet - Page 80
    Thermal Specifications and Design Considerations Table 5-5. Intel® Core™2 Quad Processor Q9000S and Q8000S Series Thermal Profile Power Maximum (W) Tc (°C) 0 49.6 2 50.4 4 51.2 6 52.1 8 52.9 10 53.7 12 54.5 14 55.3 16 56.2 Power Maximum (W) Tc (°C) 18 57.0 20 57.8 22 58.6
  • Intel Q9400S | Data Sheet - Page 81
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel Q9400S | Data Sheet - Page 82
    (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and
  • Intel Q9400S | Data Sheet - Page 83
    ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the
  • Intel Q9400S | Data Sheet - Page 84
    must be designed to ensure the processor remains within specification. If the processor enters one of the above low-power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low-power state and the processor DTS temperature drops below the thermal trip
  • Intel Q9400S | Data Sheet - Page 85
    Control Interface (PECI) Specification. 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems Fan speed control solutions based on PECI utilize a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though
  • Intel Q9400S | Data Sheet - Page 86
    that fall under the specification, the PECI will always Support The error codes supported for the processor GetTemp() command are listed in Table 5-6. Table 5-6. GetTemp0() Error Codes Error Code Description 8000h 8002h General sensor error Sensor is operational, but has detected a temperature
  • Intel Q9400S | Data Sheet - Page 87
    the EXT_CONFIG Model Specific Register (MSR). This MSR allows for the disabling of a single core per die within the processor package. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop-Grant states to reduce power consumption by stopping the clock
  • Intel Q9400S | Data Sheet - Page 88
    INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more
  • Intel Q9400S | Data Sheet - Page 89
    processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown must be enabled using the BIOS for the processor to remain within its specification. The processor The processor supports the Stop
  • Intel Q9400S | Data Sheet - Page 90
    serviced the processor will return to the Extended HALT state or Extended Stop Grant state. Sleep State The Sleep state is a low power state in which the processor the processor is not in these states is out of specification and may result in unapproved operation. In the Sleep state, the processor is
  • Intel Q9400S | Data Sheet - Page 91
    processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate similar to the Deep Sleep state but the core voltage is reduced to a lower level.
  • Intel Q9400S | Data Sheet - Page 92
    technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled. Enhanced Intel SpeedStep Technology is a technology that creates processor performance states (P states). P states are power consumption and capability states within the
  • Intel Q9400S | Data Sheet - Page 93
    Boxed Processor Specifications 7 Boxed Processor Specifications 7.1 Introduction The Intel Core™2 Extreme processor QX9650, Intel Core™2 quad-core processor Q9000, Q9000S, Q8000, and Q8000S series will also be offered as an Intel boxed processor. Intel boxed processors are intended for system
  • Intel Q9400S | Data Sheet - Page 94
    Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow
  • Intel Q9400S | Data Sheet - Page 95
    power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 7-5. Baseboards must provide a matched power header to support the boxed processor. Table 7-1 contains specifications
  • Intel Q9400S | Data Sheet - Page 96
    Figure 7-6 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket. Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description Pin Signal 1 GND
  • Intel Q9400S | Data Sheet - Page 97
    system, and ultimately the responsibility of the system integrator. The processor temperature specification is in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 5-1) in chassis that provide good thermal management. For
  • Intel Q9400S | Data Sheet - Page 98
    degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to
  • Intel Q9400S | Data Sheet - Page 99
    Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines (See Section 1.2). Boxed Intel® Core™2 Extreme Processor QX9650 Specifications
  • Intel Q9400S | Data Sheet - Page 100
    Figure 7-10. Space Requirements for the Boxed Processor (side view) 7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight The Boxed Intel® Core™2 Extreme processor QX9650 fan heatsink weight will complies with the socket specifications. See Chapter 5 and the appropriate Thermal
  • Intel Q9400S | Data Sheet - Page 101
    Boxed Processor Specifications Figure 7-12. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) § Datasheet 103
  • Intel Q9400S | Data Sheet - Page 102
    Boxed Processor Specifications 104 Datasheet
  • Intel Q9400S | Data Sheet - Page 103
    Intel® Core™2 Extreme processor QX9000 series, Intel® Core™2 Quad processor Q9000, Q9000S, Q8000, and Q8000S series systems. Tektronix and Agilent should be contacted to get specific Electrical Considerations The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
  • Intel Q9400S | Data Sheet - Page 104
    Debug Tools Specifications 106 Datasheet
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Document Number: 318726-010
Intel
®
Core™2 Extreme Processor
QX9000
Δ
Series, Intel
®
Core™2 Quad
Processor Q9000
Δ
, Q9000S
Δ
, Q8000
Δ
,
and Q8000S
Δ
Series
Datasheet
— on 45 nm process in the 775 land package
August 2009