Intel Q9400S Data Sheet - Page 59

Land Listing and Signal Descriptions

Datasheet

59

B12

D13#

Source Synch

Input/Output

B13

COMP8

Power/Other

Input

B14

VSS

Power/Other

B15

D53#

Source Synch

Input/Output

B16

D55#

Source Synch

Input/Output

B17

VSS

Power/Other

B18

D57#

Source Synch

Input/Output

B19

D60#

Source Synch

Input/Output

B2

DBSY#

Common Clock

Input/Output

B3

RS0#

Common Clock

Input

B4

D00#

Source Synch

Input/Output

B5

VSS

Power/Other

B6

D05#

Source Synch

Input/Output

B7

D06#

Source Synch

Input/Output

B8

VSS

Power/Other

B9

DSTBP0#

Source Synch

Input/Output

B20

VSS

Power/Other

B21

D59#

Source Synch

Input/Output

B22

D63#

Source Synch

Input/Output

B23

VSSA

Power/Other

B24

VSS

Power/Other

B25

VTT

Power/Other

B26

VTT

Power/Other

B27

VTT

Power/Other

B28

VTT

Power/Other

B29

VTT

Power/Other

B30

VTT

Power/Other

C1

DRDY#

Common Clock

Input/Output

C2

BNR#

Common Clock

Input/Output

C3

LOCK#

Common Clock

Input/Output

C4

VSS

Power/Other

C5

D01#

Source Synch

Input/Output

C6

D03#

Source Synch

Input/Output

C7

VSS

Power/Other

C8

DSTBN0#

Source Synch

Input/Output

C9

BPMb1#

Common Clock

Input/Output

C10

VSS

Power/Other

C11

D11#

Source Synch

Input/Output

C12

D14#

Source Synch

Input/Output

C13

VSS

Power/Other

C14

D52#

Source Synch

Input/Output

C15

D51#

Source Synch

Input/Output

C16

VSS

Power/Other

C17

DSTBP3#

Source Synch

Input/Output

C18

D54#

Source Synch

Input/Output

C19

VSS

Power/Other

Table 4-2.

Numerical Land

Assignment

Land

#

Land Name

Signal Buffer

Type

Direction

C20

DBI3#

Source Synch

Input/Output

C21

D58#

Source Synch

Input/Output

C22

VSS

Power/Other

C23

VCCIOPLL

Power/Other

C24

VSS

Power/Other

C25

VTT

Power/Other

C26

VTT

Power/Other

C27

VTT

Power/Other

C28

VTT

Power/Other

C29

VTT

Power/Other

C30

VTT

Power/Other

D1

RESERVED

D2

ADS#

Common Clock

Input/Output

D3

VSS

Power/Other

D4

HIT#

Common Clock

Input/Output

D5

VSS

Power/Other

D6

VSS

Power/Other

D7

D20#

Source Synch

Input/Output

D8

D12#

Source Synch

Input/Output

D9

VSS

Power/Other

D10

D22#

Source Synch

Input/Output

D11

D15#

Source Synch

Input/Output

D12

VSS

Power/Other

D13

D25#

Source Synch

Input/Output

D14

RESERVED

D15

VSS

Power/Other

D16

RESERVED

D17

D49#

Source Synch

Input/Output

D18

VSS

Power/Other

D19

DBI2#

Source Synch

Input/Output

D20

D48#

Source Synch

Input/Output

D21

VSS

Power/Other

D22

D46#

Source Synch

Input/Output

D23

VCCPLL

Power/Other

D24

VSS

Power/Other

D25

VTT

Power/Other

D26

VTT

Power/Other

D27

VTT

Power/Other

D28

VTT

Power/Other

D29

VTT

Power/Other

D30

VTT

Power/Other

E2

VSS

Power/Other

E3

TRDY#

Common Clock

Input

E4

HITM#

Common Clock

Input/Output

E5

FC20

Power/Other

E6

RESERVED

Table 4-2.

Numerical Land

Assignment

Land

#

Land Name

Signal Buffer

Type

Direction

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

Intel Q9400S Data Sheet - Page 59

Datasheet, Source Synch, Input/Output, COMP8, Power/Other, Input, Common Clock, DSTBP0, DSTBN0,

Page 59 highlights