Intel Q9400S Data Sheet - Page 23

Notes

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Electrical Specifications Table 2-4. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.38 mΩ Minimum Voltage 1.45 mΩ 0 0.000 5 -0.007 10 -0.013 -0.019 -0.026 -0.033 -0.038 -0.045 -0.053 15 -0.020 -0.040 -0.060 20 -0.026 -0.047 -0.067 25 -0.033 -0.053 -0.074 30 -0.039 -0.060 -0.082 35 -0.046 40 -0.052 45 -0.059 50 -0.065 55 -0.072 -0.067 -0.074 -0.081 -0.088 -0.095 -0.089 -0.096 -0.103 -0.111 -0.118 60 -0.078 -0.102 -0.125 65 -0.085 -0.108 -0.132 70 -0.091 -0.115 -0.140 75 -0.098 -0.122 -0.147 80 -0.101 -0.126 -0.151 85 -0.111 90 -0.117 95 -0.124 100 -0.130 105 -0.137 -0.136 -0.143 -0.150 -0.157 -0.163 -0.161 -0.169 -0.176 -0.183 -0.190 110 -0.143 -0.170 -0.198 115 -0.150 -0.177 -0.205 120 -0.156 125 -0.163 -0.184 -0.191 -0.212 -0.219 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This table is intended to aid in reading discrete points on Figure 2-1. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation. Datasheet 23

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Datasheet
23
Electrical Specifications
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in
Section 2.6.3
.
2.
This table is intended to aid in reading discrete points on
Figure 2-1
.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator Design Guide for socket
loadline guidelines and VR implementation details.
4.
Adherence to this loadline specification is required to ensure reliable processor operation.
Table 2-4.
V
CC
Static and Transient Tolerance
I
CC
(A)
Voltage Deviation from VID Setting (V)
1, 2, 3, 4
Maximum Voltage
1.30 m
Ω
Typical Voltage
1.38 m
Ω
Minimum Voltage
1.45 m
Ω
0
0.000
-0.019
-0.038
5
-0.007
-0.026
-0.045
10
-0.013
-0.033
-0.053
15
-0.020
-0.040
-0.060
20
-0.026
-0.047
-0.067
25
-0.033
-0.053
-0.074
30
-0.039
-0.060
-0.082
35
-0.046
-0.067
-0.089
40
-0.052
-0.074
-0.096
45
-0.059
-0.081
-0.103
50
-0.065
-0.088
-0.111
55
-0.072
-0.095
-0.118
60
-0.078
-0.102
-0.125
65
-0.085
-0.108
-0.132
70
-0.091
-0.115
-0.140
75
-0.098
-0.122
-0.147
80
-0.101
-0.126
-0.151
85
-0.111
-0.136
-0.161
90
-0.117
-0.143
-0.169
95
-0.124
-0.150
-0.176
100
-0.130
-0.157
-0.183
105
-0.137
-0.163
-0.190
110
-0.143
-0.170
-0.198
115
-0.150
-0.177
-0.205
120
-0.156
-0.184
-0.212
125
-0.163
-0.191
-0.219