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Intel Q9400S Data Sheet - Page 65

Table 4-3., Signal Description, Sheet 2 of 10

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Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 10) Name Type Description BPM[5:0]# BPMb[3:0]# BPRI# BR0# BSEL[2:0] COMP[3:0], COMP8 Input/ Output Input Input/ Output Output Analog BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# and BPMb[3:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[3:0]# are associated with core 0. BPMb[3:0]# are associated with core 1. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. These signals do not have on-die termination. Refer to Section 2.6.2 for termination requirements. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 2-15 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to Section 2.8.2. COMP[3:0] and COMP8 must be terminated to VSS on the system board using precision resistors. Datasheet 65

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

Match case Limit results 1 per page

Land Listing and Signal Descriptions

Datasheet

BPM[5:0]#

BPMb[3:0]#

Input/

Output

BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint

and performance monitor signals. They are outputs from the

processor which indicate the status of breakpoints and

programmable counters used for monitoring processor

performance. BPM[5:0]# and BPMb[3:0]# should connect the

appropriate pins/lands of all processor FSB agents. BPM[3:0]# are

associated with core 0. BPMb[3:0]# are associated with core 1.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP

port. PRDY# is a processor output used by debug tools to

determine processor debug readiness.

BPM5# provides PREQ# (Probe Request) functionality for the TAP

port. PREQ# is used by debug tools to request debug operation of

the processor.

These signals do not have on-die termination. Refer to

Section 2.6.2

for termination requirements.

BPRI#

Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of

the processor FSB. It must connect the appropriate pins/lands of

all processor FSB agents. Observing BPRI# active (as asserted by

the priority agent) causes all other agents to stop issuing new

requests, unless such requests are part of an ongoing locked

operation. The priority agent keeps BPRI# asserted until all of its

requests are completed, then releases the bus by de-asserting

BPRI#.

BR0#

Input/

Output

BR0# drives the BREQ0# signal in the system and is used by the

processor to request the bus. During power-on configuration this

signal is sampled to determine the agent ID = 0.

This signal does not have on-die termination and must be

terminated.

BSEL[2:0]

Output

The BCLK[1:0] frequency select signals BSEL[2:0] are used to

select the processor input clock frequency.

Table 2-15

defines the

possible combinations of the signals and the frequency associated

with each combination. The required frequency is determined by

the processor, chipset and clock synthesizer. All agents must

operate at the same frequency. For more information about these

signals, including termination recommendations refer to

Section 2.8.2

COMP[3:0],

COMP8

Analog

COMP[3:0] and COMP8 must be terminated to V

on the system

board using precision resistors.

Table 4-3.

Signal Description

(Sheet 2 of 10)

Name

Type

Description