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Intel Q9400S Data Sheet - Page 27

Table 2-6., FSB Signal Groups Sheet 2 of 2, Table 2-7., Signal Characteristics, Table 2-8., Signal

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Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals1 GTL+ Strobes CMOS Open Drain Output Open Drain Input/Output FSB Clock Power/Other Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/ INTR, LINT1/NMI, SMI#3, STPCLK#, PWRGOOD, SLP#, TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0], PSI# FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M Clock PROCHOT#4 BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[10,7:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0] . Table 2-7. Table 2-8. NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. 4. PROCHOT# signal type is open drain output and CMOS input. Signal Characteristics Signals with RTT A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY# Signals with No RTT A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/ NMI, MSID[1:0], PWRGOOD, RESET#, SMI#, STPCLK#, TDO, TDO_M, TESTHI[10,7:0], THERMTRIP#, VID[7:0], GTLREF[3:0], TCK, TDI, TDI_M, TMS, TRST#, VTT_SEL Open Drain Signals1 THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BPMb[3:0]#, BR0#, TDO, TDO_M, FCx NOTES: 1. Signals that do not have RTT, nor are actively driven to their high-voltage level. Signal Reference Voltages GTLREF BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY# VTT/2 A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TDI_M1, TMS1, TRST#1 NOTE: 1. See Table 2-10 for more information. Datasheet 27

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

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Datasheet

Electrical Specifications

NOTES:

Refer to

Section 4.2

for signal descriptions.

In processor systems where no debug port is implemented on the system board, these

signals are used to support a debug port interposer. In systems with the debug port

implemented on the system board, these signals are no connects.

The value of these signals during the active-to-inactive edge of RESET# defines the

processor configuration options. See

Section 6.1

for details.

PROCHOT# signal type is open drain output and CMOS input.

NOTES:

Signals that do not have R

, nor are actively driven to their high-voltage level.

NOTE:

See

Table 2-10

for more information.

GTL+ Strobes

Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS

A20M#, DPSLP#, DPRSTP#, IGNNE#, INIT#, LINT0/

INTR, LINT1/NMI, SMI#

, STPCLK#, PWRGOOD, SLP#,

TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],

PSI#

Open Drain

Output

FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M

Open Drain

Input/Output

PROCHOT#

FSB Clock

Clock

BCLK[1:0], ITP_CLK[1:0]

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,

GTLREF[3:0], COMP[8,3:0], RESERVED, TESTHI[10,7:0],

VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,

VSS_MB_REGULATION, DBR#

, VTT_OUT_LEFT,

VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]

Table 2-6.

FSB Signal Groups (Sheet 2 of 2)

Signal Group

Type

Signals

Table 2-7.

Signal Characteristics

Signals with R

Signals with No R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,

HITM#, LOCK#, PROCHOT#, REQ[4:0]#,

RS[2:0]#, TRDY#

A20M#, BCLK[1:0], BSEL[2:0],

COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,

INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/

NMI, MSID[1:0], PWRGOOD, RESET#, SMI#,

STPCLK#, TDO, TDO_M, TESTHI[10,7:0],

THERMTRIP#, VID[7:0], GTLREF[3:0], TCK,

TDI, TDI_M, TMS, TRST#, VTT_SEL

Open Drain Signals

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,

BPMb[3:0]#, BR0#, TDO, TDO_M, FCx

Table 2-8.

Signal Reference Voltages

GTLREF

BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#,

HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,

BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,

DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,

REQ[4:0]#, RS[2:0]#, TRDY#

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,

INIT#, PROCHOT#, PWRGOOD

, SMI#,

STPCLK#, TCK

, TDI

, TDI_M

, TMS

TRST#