Intel Q9400S Data Sheet - Page 47

Land Listing and Signal Descriptions

Datasheet

47

D32#

G16

Source Synch

Input/Output

D33#

E15

Source Synch

Input/Output

D34#

E16

Source Synch

Input/Output

D35#

G18

Source Synch

Input/Output

D36#

G17

Source Synch

Input/Output

D37#

F17

Source Synch

Input/Output

D38#

F18

Source Synch

Input/Output

D39#

E18

Source Synch

Input/Output

D40#

E19

Source Synch

Input/Output

D41#

F20

Source Synch

Input/Output

D42#

E21

Source Synch

Input/Output

D43#

F21

Source Synch

Input/Output

D44#

G21

Source Synch

Input/Output

D45#

E22

Source Synch

Input/Output

D46#

D22

Source Synch

Input/Output

D47#

G22

Source Synch

Input/Output

D48#

D20

Source Synch

Input/Output

D49#

D17

Source Synch

Input/Output

D50#

A14

Source Synch

Input/Output

D51#

C15

Source Synch

Input/Output

D52#

C14

Source Synch

Input/Output

D53#

B15

Source Synch

Input/Output

D54#

C18

Source Synch

Input/Output

D55#

B16

Source Synch

Input/Output

D56#

A17

Source Synch

Input/Output

D57#

B18

Source Synch

Input/Output

D58#

C21

Source Synch

Input/Output

D59#

B21

Source Synch

Input/Output

D60#

B19

Source Synch

Input/Output

D61#

A19

Source Synch

Input/Output

D62#

A22

Source Synch

Input/Output

D63#

B22

Source Synch

Input/Output

DBI0#

A8

Source Synch

Input/Output

DBI1#

G11

Source Synch

Input/Output

DBI2#

D19

Source Synch

Input/Output

DBI3#

C20

Source Synch

Input/Output

DBR#

AC2

Power/Other

Output

DBSY#

B2

Common Clock

Input/Output

DEFER#

G7

Common Clock

Input

DPRSTP#

T2

Asynch CMOS

Input

DPSLP#

P1

Asynch CMOS

Input

DRDY#

C1

Common Clock

Input/Output

DSTBN0#

C8

Source Synch

Input/Output

DSTBN1#

G12

Source Synch

Input/Output

DSTBN2#

G20

Source Synch

Input/Output

DSTBN3#

A16

Source Synch

Input/Output

Table 4-1.

Alphabetical Land

Assignments

Land Name

Land #

Signal Buffer

Type

Direction

DSTBP0#

B9

Source Synch

Input/Output

DSTBP1#

E12

Source Synch

Input/Output

DSTBP2#

G19

Source Synch

Input/Output

DSTBP3#

C17

Source Synch

Input/Output

FC0/

BOOTSELECT

Y1

Power/Other

FC3

J2

Power/Other

FC8

AK6

Power/Other

FC10

E24

Power/Other

FC15

H29

Power/Other

FC18

AE3

Power/Other

FC20

E5

Power/Other

FC21

F6

Power/Other

FC22

J3

Power/Other

FC23

A24

Power/Other

FC24

AK1

Power/Other

FC25

AL1

Power/Other

FC26

E29

Power/Other

FC29

U2

Power/Other

FC30

U3

Power/Other

FC31

J16

Power/Other

FC32

H15

Power/Other

FC33

H16

Power/Other

FC34

J17

Power/Other

FC35

H4

Power/Other

FC36

AD3

Power/Other

FC37

AB3

Power/Other

FC39

AA2

Power/Other

FC40

AM6

Power/Other

FERR#/PBE#

R3

Asynch CMOS

Output

GTLREF0

H1

Power/Other

Input

GTLREF1

H2

Power/Other

Input

GTLREF2

F2

Power/Other

Input

GTLREF3

G10

Power/Other

Input

HIT#

D4

Common Clock

Input/Output

HITM#

E4

Common Clock

Input/Output

IERR#

AB2

Asynch CMOS

Output

IGNNE#

N2

Asynch CMOS

Input

INIT#

P3

Asynch CMOS

Input

ITP_CLK0

AK3

TAP

Input

ITP_CLK1

AJ3

TAP

Input

LINT0

K1

Asynch CMOS

Input

LINT1

L1

Asynch CMOS

Input

LOCK#

C3

Common Clock

Input/Output

MSID0

W1

Power/Other

Output

MSID1

V1

Power/Other

Output

Table 4-1.

Alphabetical Land

Assignments

Land Name

Land #

Signal Buffer

Type

Direction

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

Intel Q9400S Data Sheet - Page 47

Land Listing and Signal Descriptions

Page 47 highlights