Intel Q9400S Data Sheet - Page 31

Electrical Specifications 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.5 (see Table 2-14 for the processor supported ratios). The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency 1/6 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10 1/10.5 1/11 1/11.5 1/12 1/12.5 1/13 1/13.5 1/14 1/15 Core Frequency (333 MHz BCLK/ 1333 MHz FSB) 2 GHz 2.33 GHz 2.50 GHz 2.66 GHz 2.83 GHz 3 GHz 3.16 GHz 3.33 GHz 3.50 GHz 3.66 GHz 3.83 GHz 4 GHz 4.16 GHz 4.33 GHz 4.50 GHz 4.66 GHz 5 GHz Core Frequency (400 MHz BCLK/ 1600 MHz FSB) 2.6 GHz 2.8 GHz 3.0 GHz 3.2 GHz 3.4 GHz 3.6 GHz 3.8 GHz 4.0 GHz 4.2 GHz 4.4 GHz 4.6 GHz 4.8 GHz 5.0 GHz 5.2 GHz 5.4 GHz 5.6 GHz 5.8 GHz NOTES: 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. Notes1, 2 - Datasheet 31