Home » Intel Manuals » Processors » Intel Q9400S » Manual Viewer

Intel Q9400S Data Sheet - Page 28

CMOS and Open Drain Signals, Processor DC Specifications

UPC - 735858207973

Add to My Manuals
Save this manual to your list of manuals

Page 28 highlights

Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/ deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 2-9. GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL VIH VOH IOL ILI ILO RON Input Low Voltage -0.10 GTLREF - 0.10 V Input High Voltage GTLREF + 0.10 VTT + 0.10 V Output High Voltage VTT - 0.10 VTT V Output Low Current N/A VTT_MAX / [(RTT_MIN) + (2 * RON_MIN)] A Input Leakage Current N/A ± 100 µA Output Leakage Current N/A ± 100 µA Buffer On Resistance 7.5 11 Ω 2, 5 3, 4, 5 4, 5 - 6 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VTT. 5. The VTT referred to in these specifications is the instantaneous VTT. 6. Leakage to VSS with land held at VTT. 7. Leakage to VTT with land held at 300 mV. Table 2-10. Open Drain and TAP Output Signal Group DC Specifications Symbol Parameter Min Max VOL Output Low Voltage IOL Output Low Current ILO Output Leakage Current 0 0.20 16 50 N/A ± 200 Unit Notes1 V - mA 2 µA 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at VTT * 0.2V. 3. For Vin between 0 and VOH. 28 Datasheet

Section	Page
Intel® Core™2 Extreme Processor QX9000D Series, Intel® Core™2 Quad Processor Q9000D, Q9000SD, Q8000D, and Q8000SD Series	1
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor QX9000 Series and Intel® Core™2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology Definitions	12
1.2 References	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
2.4 Reserved, Unused, and TESTHI Signals	18
2.5 Power Segment Identifier (PSID)	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
2.6.2 DC Voltage and Current Specification	20
2.6.3 VCC Overshoot	25
2.6.4 Die Voltage Validation	25
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	26
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	28
2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications	29
2.7.3.2 GTL+ Front Side Bus Specifications	30
2.8 Clock Specifications	31
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
2.8.2 FSB Frequency Select Signals (BSEL[2:0])	32
2.8.3 Phase Lock Loop (PLL) and Filter	32
2.8.4 BCLK[1:0] Specifications	32
3 Package Mechanical Specifications	35
3.1 Package Mechanical Drawing	35
3.2 Processor Component Keep-Out Zones	39
3.3 Package Loading Specifications	39
3.4 Package Handling Guidelines	39
3.5 Package Insertion Specifications	40
3.6 Processor Mass Specification	40
3.7 Processor Materials	40
3.8 Processor Markings	40
4 Land Listing and Signal Descriptions	43
4.1 Processor Land Assignments	43
4.2 Alphabetical Signals Reference	64
5 Thermal Specifications and Design Considerations	75
5.1 Processor Thermal Specifications	75
5.1.1 Thermal Specifications	75
5.1.2 Thermal Metrology	81
5.2 Processor Thermal Features	81
5.2.1 Thermal Monitor	81
5.2.2 Thermal Monitor 2	82
5.2.3 On-Demand Mode	83
5.2.4 PROCHOT# Signal	84
5.2.5 THERMTRIP# Signal	84
5.3 Platform Environment Control Interface (PECI)	85
5.3.1 Introduction	85
5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems	85
5.3.2 PECI Specifications	86
5.3.2.1 PECI Device Address	86
5.3.2.2 PECI Command Support	86
5.3.2.3 PECI Fault Handling Requirements	86
5.3.2.4 PECI GetTemp0() Error Code Support	86
6 Features	87
6.1 Power-On Configuration Options	87
6.2 Clock Control and Low Power States	87
6.2.1 Normal State	88
6.2.2 HALT and Extended HALT Powerdown States	88
6.2.2.1 HALT Powerdown State	88
6.2.2.2 Extended HALT Powerdown State	89
6.2.3 Stop Grant and Extended Stop Grant States	89
6.2.3.1 Stop-Grant State	89
6.2.3.2 Extended Stop Grant State	90
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	90
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	90
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	90
6.2.5 Sleep State	90
6.2.6 Deep Sleep State	91
6.2.7 Deeper Sleep State	91
6.2.8 Enhanced Intel SpeedStep® Technology	92
6.3 Processor Power Status Indicator (PSI) Signal	92
7 Boxed Processor Specifications	93
7.1 Introduction	93
7.2 Mechanical Specifications	94
7.2.1 Boxed Processor Cooling Solution Dimensions	94
7.2.2 Boxed Processor Fan Heatsink Weight	95
7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	95
7.3 Electrical Requirements	95
7.3.1 Fan Heatsink Power Supply	95
7.4 Thermal Specifications	97
7.4.1 Boxed Processor Cooling Requirements	97
7.4.2 Variable Speed Fan	98
7.5 Boxed Intel® Core™2 Extreme Processor QX9650 Specifications	99
7.5.1 Boxed Intel® Core™2 Extreme Processor QX9650 Fan Heatsink Weight	100
8 Debug Tools Specifications	103
8.1 Logic Analyzer Interface (LAI)	103
8.1.1 Mechanical Considerations	103

Match case Limit results 1 per page

Electrical Specifications

Datasheet

2.7.2

CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS

input buffers. All of the CMOS and Open Drain signals are required to be asserted/

deasserted for at least eight BCLKs in order for the processor to recognize the proper

signal state. See

Section 2.7.3

for the DC specifications. See

Section 6.2

for additional

timing requirements for entering and leaving the low power states.

2.7.3

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)

unless otherwise stated. All specifications apply to all frequencies and cache sizes

unless otherwise stated.

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

is defined as the voltage range at a receiving agent that will be interpreted as a logical

low value.

is defined as the voltage range at a receiving agent that will be interpreted as a logical

high value.

and V

may experience excursions above V

The V

referred to in these specifications is the instantaneous V

Leakage to V

with land held at V

Leakage to V

with land held at 300 mV.

NOTES:

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Measured at V

* 0.2V.

For Vin between 0 and V

Table 2-9.

GTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

Input Low Voltage

-0.10

GTLREF – 0.10

2, 5

Input High Voltage

GTLREF + 0.10

+ 0.10

3, 4, 5

Output High Voltage

– 0.10

4, 5

Output Low Current

N/A

TT_MAX

[(R

TT_MIN

) + (2 * R

ON_MIN

)]

Input Leakage

Current

N/A

± 100

μA

Output Leakage

Current

N/A

± 100

μA

Buffer On Resistance

7.5

Table 2-10.

Open Drain and TAP Output Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes

Output Low Voltage

0.20

Output Low Current

Output Leakage Current

N/A

± 200

μA