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Event Status and Event Status Enable Registers

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8808A Users Manual UQCDEOPRsuxoepoeeeveeirmwrqrccyeuaumrRteteiiaEesorontODqrnndneuoCrpeCEEoersrotrnrntoormdrropellnetteError Logical OR 7 65432 10 Standard Event Status Register & & &&& & && Read Using *ESR? Standard Queue Not-Empty 7 6 5 4 3 2 1 0 Event Status Enable Register Read Using *ESE? Write to Using *ESE Output Queue Service Request Generation Logical OR RQS 7 6 3 ESB MAV 2 1 0 MSS & & && & && 7 5432 10 Read by Serial Poll Status Byte Register Read Using *STB? Service Request Enable Register Read Using *SRE? Write to Using *SRE Figure 4-2. Overview of Status Data Structures aam21f.eps Event Status and Event Status Enable Registers The ESR assigns specified events to specific bits. (See Figure 4-3 and Table 4-6.) When a bit in the ESR is set to 1, the event that corresponds to that bit occurred after the register was last read or cleared. For example, if bit 3 (DDE) is set to 1, a device-dependent error has occurred. 4-12

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8808A
Users Manual
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Event Status Register
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Event Status Enable
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Write to Using *ESE
Power On
User Request
Command Error
Execution Error
Device Dependent Error
Query Error
Request Control
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aam21f.eps
Figure 4-2. Overview of Status Data Structures
Event Status and Event Status Enable Registers
The ESR assigns specified events to specific bits. (See Figure 4-3 and Table 4-6.) When a
bit in the ESR is set to 1, the event that corresponds to that bit occurred after the register
was last read or cleared. For example, if bit 3 (DDE) is set to 1, a device-dependent error
has occurred.