Intel SE7505VB2 Product Specification - Page 17

Processor VRD, Reset Configuration Logic, Processor Module Presence Detection, Interrupts and APIC - manual

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Intel® Server Board SE7505VB2 Functional Architecture In addition to the circuitry described above, the processor subsystem contains the following: Reset configuration logic Processor module presence detection logic Server management registers and sensors 3.1.1.1 Processor VRD The Intel Server Board SE7505VB2 has a single VRD (Voltage Regulator Down) to support two processors. It is compliant with the VRM 9.1 specification and provides a maximum of 130 AMPs, which is capable of supporting the requirements for two Intel® Xeon™ processors. The board hardware and PMC (Power Management Controller) must read the processor VID (voltage identification) bits for each processor before turning on the VRD. If the VIDs of the two processors are not identical, then the PMC will not turn on the VRD. 3.1.1.2 Reset Configuration Logic The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. The requirements are as follows: All processors in the system must operate at the same frequency, have the same cache sizes, and same VID. No mixing of product families is supported. Processors run at a fixed speed and cannot be programmed to operate at a lower or higher speed. The processor information is read at every system power-on. Note: The processor speed is the processor power on reset default value. No manual processor speed setting options exist either in the form of a BIOS setup option or jumpers. 3.1.1.3 Processor Module Presence Detection Logic is provided on the baseboard to detect the presence and identity of installed processors. The PMC checks the logic and will not turn on the system DC power unless the VIDs of both the processors match in a DP configuration. 3.1.1.4 Interrupts and APIC Interrupt generation and notification to the processors is done by the APICs in the ICH4 and the P64H2 using messages on the front side bus. 3.1.2 Memory Subsystem The baseboard supports up to four DIMM slots for a maximum memory capacity of 8 GB. The DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at 266MT/s. The memory controller supports memory scrubbing, single-bit error correction and multiple-bit error detection and Intel x4 SDDC support with x4 DIMMs. Memory can be implemented with either single sided (one row) or double-sided (two row) DIMMs. Revision 1.2 17 Intel part number C32194-002

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Intel® Server Board SE7505VB2
Functional Architecture
In addition to the circuitry described above, the processor subsystem contains the following:
±
Reset configuration logic
±
Processor module presence detection logic
±
Server management registers and sensors
3.1.1.1
Processor VRD
The Intel Server Board SE7505VB2 has a single VRD (Voltage Regulator Down) to support two
processors. It is compliant with the VRM 9.1 specification and provides a maximum of
130
AMPs, which is capable of supporting the requirements for two Intel
®
Xeon™ processors.
The board hardware and PMC (Power Management Controller) must read the processor VID
(voltage identification) bits for each processor before turning on the VRD. If the VIDs of the two
processors are not identical, then the PMC will not turn on the VRD.
3.1.1.2
Reset Configuration Logic
The BIOS determines the processor stepping, cache size, etc through the CPUID instruction.
The requirements are as follows:
±
All processors in the system must operate at the same frequency, have the same cache
sizes, and same VID. No mixing of product families is supported.
±
Processors run at a fixed speed and cannot be programmed to operate at a lower or
higher speed.
The processor information is read at every system power-on.
Note:
The processor speed is the processor power on reset default value. No manual processor
speed setting options exist either in the form of a BIOS setup option or jumpers.
3.1.1.3
Processor Module Presence Detection
Logic is provided on the baseboard to detect the presence and identity of installed processors.
The PMC checks the logic and will not turn on the system DC power unless the VIDs of both the
processors match in a DP configuration.
3.1.1.4
Interrupts and APIC
Interrupt generation and notification to the processors is done by the APICs in the ICH4 and the
P64H2 using messages on the front side bus.
3.1.2
Memory Subsystem
The baseboard supports up to four DIMM slots for a maximum memory capacity of 8 GB. The
DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at
266MT/s. The memory controller supports memory scrubbing, single-bit error correction and
multiple-bit error detection and Intel x4 SDDC support with x4 DIMMs. Memory can be
implemented with either single sided (one row) or double-sided (two row) DIMMs.
Revision 1.2
Intel part number C32194-002
17