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Intel SE7505VB2 Product Specification - Page 26

Compatibility Interrupt Control, APIC, General Purpose Input and Output Pins, Functional Architecture

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Functional Architecture Intel® Server Board SE7505VB2 3.2.4.4 Compatibility Interrupt Control The ICH4 provides the functionality of two 82C59 PIC devices for ISA-compatible interrupt handling. 3.2.4.5 APIC The ICH4 integrates an I/O APIC capability with 24 interrupts. 3.2.4.6 General Purpose Input and Output Pins The ICH4 provides a number of general purpose input and output pins. Many of these pins have alternate functions, and thus all are not available. The following table lists the GPI and GPO pins used on the board and gives a brief description of their function. Table 5. ICH4 GPIO Usage Table Pin Name (Powe Well) Used As GPI0 / REQA# (Core) BUS P1 Parity DETECT (P1_PERR#) GPI1 / REQB# (Core) BUS P2/ICH4 Parity DETECT (P2_PERR#) GPI2 / PIRQE# (Core) GPI3 / PIRQF# (Core) GPI4 / PIRQG# (Core) GPI5 / PIRQH# (Core) GPI6 (Core) PIRQ_E PIRQ_F PIRQ_G PIRQ_H IDE ATA66/100 Detect (IDES_DET) GPI7 (Core) IDE ATA66/100 Detect (IDEP_DET) GPI8 (Resume) CPU_HOT# GPI9 ~ GPI10 GPI11 NC (Resume) GPI / GPO / Function GPI GPI Function Select GPIO:R00h[0]=1 (GPIO) (GPIO:R04h[0] always = 1) GPIO:R2Ch[0]=1 (Active Low) GPIO:R00h[1]=1 (GPIO) (GPIO:R04h[1] always = 1) GPIO:R2Ch[1]=1 (Active Low) GPIO:R00h[2]=0 (PIRQ_E) Data. PM:R2Eh[0] PM:R2Eh[1] GPIO:R00h[3]=0 (PIRQ_F) GPIO:R00h[4]=0 (PIRQ_G) GPIO:R00h[5]=0 (PIRQ_H) GPI (GPIO:R04h[6] always = 1) PM:R2Eh[6] GPIO:R2Ch[6]=0 (Active High) GPI (GPIO:R04h[7] always = 1) PM:R2Eh[7] GPIO:R2Ch[7]=0 (Active High) GPI (GPIO:R04h[8] always = 1) PM:R2Eh[8] GPIO:R2Ch[8]=1 (Active Low) GPI GPIO:R00h[11]=1 (GPIO) PM:R2Eh[11] (GPIO:R04h[11] always = 1) GPIO:R2Ch[11]=0 (Active High) Pin Description 1: Normal 0: SMI or SCI or Wakeup event 1: Normal 0: SMI or SCI or Wakeup Event 1: ATA33 0: ATA66/100 1: ATA33 0: ATA66/100 1: Normal 0: SMI or SCI or Wakeup Event N/A 26 Revision 1.2 Intel part number C32194-002

Section	Page
Introduction	13
SE7505VB2 Server Board Overview	14
Intel® Server Board SE7505VB2 Feature Set	14
Functional Architecture	16
Processor and Memory Subsystem	16
Processor Support	16
Processor VRD	17
Reset Configuration Logic	17
Processor Module Presence Detection	17
Interrupts and APIC	17
Memory Subsystem	17
Memory DIMM Support	18
Memory Configuration	19
Memory Cooling	19
I2C Bus	21
DRAM ECC	21
The Intel® E7505 Chipset	21
MCH Memory Architecture Overview	22
DDR Configurations	23
Memory Controller Hub (MCH)	23
AGP 8X Bus	24
P64H2	24
PCI Bus P64-B I/O Subsystem	24
PCI Bus P64-C I/O Subsystem	24
ICH4	24
PCI Bus P32-A I/O Subsystem	25
PCI Bus Master IDE Interface	25
USB Interface	25
Compatibility Interrupt Control	26
APIC	26
General Purpose Input and Output Pins	26
Power Management	28
Super I/O	28
GPIOs	29
Serial Ports	29
Serial A	29
Serial B	29
Floppy Disk Controller	30
Keyboard and Mouse	30
Wake-up Control	30
BIOS Flash	30
Clock Generation and Distribution	31
PCI I/O Subsystem	33
PCI Subsystem	33
P32-A: 32-bit/33-MHz PCI Subsystem	33
Device IDs (IDSEL)	33
P32-A Arbitration	34
P64-B and P64-C: 64-bit/100- or 66-MHz PCI Subsystem	34
Device IDs (IDSEL)	34
P64-B Arbitration	35
P64-C Arbitration	35
Serial ATA Controller	35
Video Controller	36
Video Modes	37
Video Memory Interface	37
Host Bus Interface	38
Network Interface Controller (NIC)	39
NIC Connector and Status LEDs	39
Interrupt Routing	40
Legacy Interrupt Routing	40
APIC Interrupt Routing	40
Legacy Interrupt Sources	41
Serialized IRQ Support	41
IRQ Scan for PCIIRQ	41
PCI Error Handling	41
Hardware Monitoring	45
Monitored Components	45
Fan Speed Control	46
Chassis Intrusion	46
SE7505VB2 ACPI Implementation	48
ACPI	48
Front Panel Switches	48
Wake up Sources (ACPI and Legacy)	49
SE7505VB2 Connectors	50
Main Power Connector	50
Memory Module Connector	51
Processor Socket	52
I2C Header	55
PCI Slot Connector	55
AGP 3.0 Pro50 Connector	58
Front Panel Connector	59
VGA Connector	59
NIC Connector	60
IDE Connector	60
SATA Connector	61
USB Connector	62
Floppy Connector	63
Serial Port Connector	63
Keyboard and Mouse Connector	64
Miscellaneous Headers	64
Fan Header	64
Intrusion Cable Connector	65
Configuration Jumpers	66
System Recovery and Update Jumpers	66
BIOS	67
Using the BIOS Setup Utility	67
If You Cannot Access Setup	67
Starting Setup	67
Setup Menus	67
Menu Selection Bar	69
Main Menu	70
Primary/Secondary, Master/Slave Submenus	71
Advanced Menu	72
I/O Device Configuration Submenu	73
On Board Device Submenu	76
PCI Configuration Submenu	77
Server Menu Submenu	78
Console Redirection Submenu	79
Event Logging Submenu	81
Hardware Monitor Submenu	82
Security Menu	83
Power Menu	84
Boot Menu	85
System Menu	86
Exit Menu	87
Upgrading the BIOS	88
Preparing for the Upgrade	88
Recording the Current BIOS Settings	88
Obtaining the Upgrade Utility	88
Creating a Bootable Diskette	89
Creating the BIOS Upgrade Diskette	89
Upgrading the BIOS	89
Crisis Recovery Diskette	90
Creating the Crisis Recovery Diskette	91
Manually Recovering the BIOS	92
Error Handling and Reporting	93
POST Error Beep Codes	93
BIOS Event Log	93
Absolute Maximum Ratings	94
Mean Time Between Failures (MTBF) Test Results	94
Power Information	95
SE7505VB2 Server Board Power Budget	95
Power Supply Specifications	96
Power Timing	96
Voltage Recovery Timing Specifications	99
Product Regulatory Compliance	100
	100
Product Safety Compliance	100
Product EMC Compliance	100
Mandatory / Standard: Certifications; Registration; Declarations	100
Other Product Mandatory Regulations to Consider due to new Emerging International Requirements	101
Important Product Regulation Requirements	101
Product Regulatory Compliance Markings	101
Electromagnetic Compatibility Notices	102
Europe (CE Declaration of Conformity)	102
Australian Communications Authority (ACA) (C-Tick Declaration of Conformity)	102
Ministry of Economic Development (New Zealand) Declaration of Conformity	102
BSMI (Taiwan)	102
Replacing the Back up Battery	102

Match case Limit results 1 per page

Functional Architecture

Intel® Server Board SE7505VB2

3.2.4.4

Compatibility Interrupt Control

The ICH4 provides the functionality of two 82C59 PIC devices for ISA-compatible interrupt

handling.

3.2.4.5

APIC

The ICH4 integrates an I/O APIC capability with 24 interrupts.

3.2.4.6

General Purpose Input and Output Pins

The ICH4 provides a number of general purpose input and output pins.

Many of these pins have

alternate functions, and thus all are not available.

The following table lists the GPI and GPO

pins used on the board and gives a brief description of their function.

Table 5. ICH4 GPIO Usage Table

Pin Name

(Powe Well)

Used As

GPI /

GPO /

Function

Function Select

Data.

Pin Description

GPI0 / REQA#

(Core)

BUS P1 Parity

DETECT

(P1_PERR#)

GPI

GPIO:R00h[0]=1 (GPIO)

(GPIO:R04h[0] always = 1)

GPIO:R2Ch[0]=1 (Active

Low)

PM:R2Eh[0]

1: Normal

0: SMI or SCI or

Wakeup event

GPI1 / REQB#

(Core)

BUS P2/ICH4 Parity

DETECT

(P2_PERR#)

GPI

GPIO:R00h[1]=1 (GPIO)

(GPIO:R04h[1] always = 1)

GPIO:R2Ch[1]=1 (Active

Low)

PM:R2Eh[1]

1: Normal

0: SMI or SCI or

Wakeup Event

GPI2 / PIRQE#

(Core)

PIRQ_E

GPIO:R00h[2]=0 (PIRQ_E)

GPI3 / PIRQF#

(Core)

PIRQ_F

GPIO:R00h[3]=0 (PIRQ_F)

GPI4 / PIRQG#

(Core)

PIRQ_G

GPIO:R00h[4]=0 (PIRQ_G)

GPI5 / PIRQH#

(Core)

PIRQ_H

GPIO:R00h[5]=0 (PIRQ_H)

GPI6

(Core)

IDE ATA66/100

Detect (IDES_DET)

GPI

(GPIO:R04h[6] always = 1)

GPIO:R2Ch[6]=0 (Active

High)

PM:R2Eh[6]

1: ATA33

0: ATA66/100

GPI7

(Core)

IDE ATA66/100

Detect (IDEP_DET)

GPI

(GPIO:R04h[7] always = 1)

GPIO:R2Ch[7]=0 (Active

High)

PM:R2Eh[7]

1: ATA33

0: ATA66/100

GPI8

(Resume)

CPU_HOT#

GPI

(GPIO:R04h[8] always = 1)

GPIO:R2Ch[8]=1 (Active

Low)

PM:R2Eh[8]

1: Normal

0: SMI or SCI or

Wakeup Event

GPI9 ~ GPI10

N/A

GPI11

(Resume)

GPI

GPIO:R00h[11]=1 (GPIO)

(GPIO:R04h[11] always = 1)

GPIO:R2Ch[11]=0 (Active

High)

PM:R2Eh[11]

Revision 1.2

Intel part number C32194-002