Gateway 9315 Gateway 9315 Server User Guide - Page 116

POST code checkpoints The following table shows the checkpoints, LED codes, and task description of events that may occur during the POST portion of the BIOS: Check point 03 04 05 06 08 C0 C1 C2 C5 C6 C7 0A 0B 0C Diagnostic LED decoder G=Green, R=Red, O=Orange Off Off G G Off G Off Off Off G Off G Off G G Off G Off Off Off R R Off Off R R Off G R R G Off R O Off G R O G Off R O G G G Off G Off G Off G G G G Off Off Description Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags." Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initialize data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system. Initialize the interrupt controller in hardware (generally PIC) and interrupt vector table. Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." Initialize the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. Early CPU Init Start - Disable Cache - Init Local APIC Set up boot strap processor information. Set up boot strap processor for POST. Enumerate and set up application processors. Re-enable cache for boot strap processor. Early CPU Init Exit. Initialize the 8042 compatible keyboard controller. Detect the presence of PS/2 mouse. Detect the presence of keyboard in KBC port. www.gateway.com 111