Campbell Scientific CR10 CR10 Measurement and Control - Page 79

State

2

requires all SDs

to

drop

the

Ring line

and prepare

for addressing. The

CR10 then

synchronously clocks

8

bits onto

TXD

using

CLI</HS

as a

clock.

The

least

significant

bit

is

transmitted

first

and is

always

logic

high.

Each

bit

transmitted

is stable on

the

rising edge of

CL[(HS.

The

SDs

shift

in bits from

TXD

on

the

rising edge ot

CLI(HS

provided by

the

CR10.

The CR10

can

only address one device

per

State 2

cycle.

More than one SD may respond

to the

address,

however.

State 2 ends when

the 8th bit

is

received

by

the

SD.

SDs implemented

with shift

registers decode

the

4

most

significant

bits (bits

4,5,6,

and

7)

for

an

address.

Bit

0

is always logic

high.

Bits

1, 2,

and

3

are

optionalfunction

selectors or

commands.

Addresses established

to

date are

shown

in

Table

6.6-1 and are decoded with

respect to the

TXD

line.

TABLE

6.6-1.

SD

Addresses

87 86 85 84 83 82 81

BO

SDCggPrinter

0 0 0 0 X X X

1

StorageModule

0 0 0 1 X X X

1

CRlOKeyboard

0 0 1 0 0 X X

1

CRlODisplay

0 0 1 0 1 X X

1

CrlORFModem0

0 1 1 X X X

1

EPROMStorage0

1 0 0 X X X

1

Module

STATE

3, the SD

Active

State

The SD addressed by State 2,

enters

State

3.

All other SDs enter State

4.

An

active

SD

returns

to State

1

by resetting itself, or by the

CR10

forcing

it

to

reset.

Active SDs have different acknowledgment and

communication

protocols.

Once addressed,

the

SD

is

free

to

use

the

CLI(HS,

TXD, and

RXD

lines according

to

its

protocolwith the

CR10.

The

CR10 may also pulse

the

SDE line after

addressing,

as

long as

the

CLIVHS and SDE

are not low

at

the

same time.

STATE

4, the

SD

Inactive State

The SDs not addressed by State 2 enter State

4, if not able

to

reset

themselves

(e.9., SM192

Storage

Module).

Inactive SDs ignore data on

the

TXD

line and

are

not allowed

to

use

the

CLI(HS

or

RXD

lines.

lnactive

SDs may raise

the

Ring line

to

request service.

SECTION

6.

g-PIN

SERIAL

INPUT/OUTPUT

STATE

5

State

5

is a branch

trom State

1

when

the

SDE

line is high and

the

CLI(HS

line is

low.

The

SDs must drop

the

Ring line

in

this

state.

This

state

is not used by

SDs.

The

CR10 must force

the

SDs back to

the

reset state

from

State

5

before addressing SDs.

STATE

6

State

6

is

a branch

from State

1,

like State

5,

except

the

SDE line is low and

the

CLIVHS line

is

high.

The

SDs must drop

the

Ring line

in

this

state.

6.7

MODEM/TERMINAL AND

COMPUTER REOUIREMENTS

6.7.1

SC32A

INTERFACE

The CR10 considers any device with an

asynchronous serial

communications

port which

raises

the

Ring line (and holds it high until

the

ME line

is

raised) to be a modem

peripheral.

Modems include Campbell Scientific phone

modems, and most

computers, terminals,

and

modems using

the

SC32A

Optically

lsolated

RS232Interface.

Most modem and

print peripherals

require the

SC32A

Optically lsolated RS232 Interface.

The

SC32A raises

the

CRl0's

ring line

when

it

receives characters

from a

modem, and

converts

the

CR10's logic levels

(0

V

logic

low,

5V logic high)

to RS232logic

levels.

The

SC32A 25-pin port

is

configured

as

Data

Communications

Equipment

(DCE)

(see Table

6.7-1) for direct connection

to

Data Terminal

Equipment (DTE),

which includes

most PCs

and

printers.

For

connection

to

DCE devices

such

as

modems and some

computers, a

null

modem

cable

is required.

When

the SC32A

receives

a

character from

the

terminal/computer

(pin 2),

5

V

is applied to

the

datalogger

Ring line (pin

3)

for one second or

untilthe

Modem Enable line (ME) goes high.

The.CR10

waits

approximately 40 seconds to

receive

carriage

returns,

which

it uses

to

establish baud

rate.

After

the baud

rate has

been set

the

CR10

transmits

a

carriage

return,

line

feed,

"*", and enters the Telecommunica-

tions Command State

(Section

5).

lf

the

carriage

returns are

not

received within

the

40

seconds, the

CRl0

"hangs

up".

6-5

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