HP rp7405 User Guide, Third Edition - hp rp7405/rp7410 Servers - Page 33

System Backplane, System Backplane Block Diagram, Clocks and Reset, I/O Subsystem

Get HP rp7405 PDF manuals and user guides View all HP rp7405 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 33 highlights

Introduction Detailed hp rp7405/rp7410 Description System Backplane The system backplane comprises the system clock generation logic, the system reset generation logic, DC-to-DC converters, power monitor logic, and two LBA link-to-PCI converter ASICs. It also includes connectors for attaching the cell boards, PCI backplane, MP Core I/O MP/SCSI boards, SCSI cables, bulk power, chassis fans, front panel display, intrusion switches, and the system scan card. Figure 1-8 System Backplane Block Diagram MP Core I/O MP/SCSI MP Core I/O MP/SCSI System backplane PCI backplane Cell board 0 Cell board 1 Cell boards are perpendicular to the system backplane. Bulk power supply Only half of the MP Core I/O board set connects to the system backplane. The MP/SCSI boards plug into the backplane, while the LAN/SCSI boards plug into the PCI backplane. Clocks and Reset The system backplane contains reset and clock circuitry that propagates through the whole system. The central clocks drive all major chip set clocks. Therefore, these circuits represent a system wide single point of failure. I/O Subsystem The cell board-to-I/O path runs from the CC to the SBA, from the SBA to the ropes, from the ropes to the LBA, and from the LBA to the PCI buses. The CC on each cell board communicates with one SBA over the SBA link. The SBA link consists of both an inbound and an outbound link with an effective bandwidth of approximately 1 GB/sec. The SBA converts the SBA link protocol into "ropes." The SBA can support up to 16 of these high-speed bi-directional rope links for a total aggregate bandwidth of approximately 4 GB/sec. The LBA acts as a bus bridge, supporting either one or two ropes and capable of driving either PCI-2x Turbo (33 MHz x 64 bits) or PCI-4 Twin Turbo (66 MHz x 64 bits) respectively Chapter 1 11

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
  • 129
  • 130
  • 131
  • 132
  • 133
  • 134
  • 135
  • 136
  • 137
  • 138
  • 139
  • 140
  • 141
  • 142
  • 143
  • 144
  • 145
  • 146
Chapter 1
Introduction
Detailed hp rp7405/rp7410 Description
11
System Backplane
The system backplane comprises the system clock generation logic, the system reset generation logic,
DC-to-DC converters, power monitor logic, and two LBA link-to-PCI converter ASICs. It also includes
connectors for attaching the cell boards, PCI backplane, MP Core I/O MP/SCSI boards, SCSI cables, bulk
power, chassis fans, front panel display, intrusion switches, and the system scan card.
Figure 1-8
System Backplane Block Diagram
Only half of the MP Core I/O board set connects to the system backplane. The MP/SCSI boards plug into the
backplane, while the LAN/SCSI boards plug into the PCI backplane.
Clocks and Reset
The system backplane contains reset and clock circuitry that propagates through the whole system. The
central clocks drive all major chip set clocks. Therefore, these circuits represent a system wide single point of
failure.
I/O Subsystem
The cell board-to-I/O path runs from the CC to the SBA, from the SBA to the ropes, from the ropes to the LBA,
and from the LBA to the PCI buses. The CC on each cell board communicates with one SBA over the SBA
link. The SBA link consists of both an inbound and an outbound link with an effective bandwidth of
approximately 1 GB/sec. The SBA converts the SBA link protocol into “ropes.” The SBA can support up to 16
of these high-speed bi-directional rope links for a total aggregate bandwidth of approximately 4 GB/sec. The
LBA acts as a bus bridge, supporting either one or two ropes and capable of driving either PCI-2x Turbo (33
MHz x 64 bits) or PCI-4 Twin Turbo (66 MHz x 64 bits) respectively
PCI backplane
Cell board 0
Cell board 1
System backplane
Bulk power supply
MP Core I/O
MP/SCSI
MP Core I/O
MP/SCSI
Cell boards are perpendicular
to the system backplane.