IBM 88554RU Installation Guide - Page 22
Two PCI-X bridges, Bandwidth, Calculation
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Memory controller A single memory controller, code named "Cyclone", located within the memory-board assembly. Two PCI-X bridges Two PCI-X bridges, code named "Winnipeg", one located on the PCI-X board and the other on the I/O board. These control both the PCI-X and Remote I/O. Figure 1-4 shows the various IBM XA-64 components in an x455 configuration. CPU 1 CPU 2 6.4 GBps CPU 3 CPU 4 400 MHz DDR DDR DDR DDR DDR DDR DDR DDR SMI-E SMI-E SMI-E SMI-E 64 MB L4 cache 6.4 GBps SMP scalability ports Cache and scalability controller Port 1 3.2 GBps 3.2 GBps Memory controller Port 2 3.2 GBps 200 MHz 2-way or 4-way interleaved DDR Processor-board assembly RXE Expansion Port A 66 MHz PCI-X bridge (1 GBps) 66 MHz 33 MHz Ultra320 SCSI Video 3x USB Gigabit Ethernet Serial RSA 1 GBps Bus A Memory-board assembly 1 GBps PCI-X bridge B-100 C-133 D-133 RXE Expansion Port B (1 GBps) 64-bit 64-bit 64-bit 66 MHz 100 MHz 133 MHz IBM XA-64 ("Summit") core chipset Figure 1-4 xSeries 455 system block diagram Table 1-3 shows how the bandwidths in Figure 1-4 are calculated. Table 1-3 Bus speeds From To CPUs Cache controller L4 Cache Cache controller Bandwidth 6.4 GBps 6.4 GBps Calculation 400 MHz x 128-bit data path 400 MHz x 128-bit data path 8 IBM xSeries 455 Planning and Installation Guide Eserver