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IBM XceL4 Accelerator Cache, Scalability Controller and Memory Controller.

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Specifically, in today's 32-bit processors, much of the instruction scheduling (the order in which computing instructions are executed) is done on the chip itself, leading to a great deal of overhead and slowing down overall processor performance. Moreover, today's processors are plagued by instruction flow problems since the processor often has to stop what it is doing and reconstruct the instruction flow due to inherent inefficiencies in instruction handling. EPIC makes the instruction scheduling more intelligent and handles much of the scheduling off-chip, in the compiler program, before feeding "parallelized" instructions to the Itanium 2 processor for execution. The parallelized instructions allow the chip to process a number of instructions simultaneously, increasing performance. The Itanium 2 architecture is based on EPIC technology and has the following features: - Provides faster online transaction processing - Has the capability to execute multiple instructions simultaneously - Enables faster calculations and data analysis - Allows for faster storage and movement of large models (CAD, CAE) - Speeds up simulation and rendering times For more information about the features of the Itanium 2 processor, go to: http://www.intel.com/design/itanium2 IBM XceL4 Accelerator Cache Integrated into the processor-board assembly is 64 MB of Level 4 cache, which is shown in Figure 1-4 on page 8. This XceL4 Server Accelerator Cache provides the necessary extra level of cache to maximize CPU throughput by reducing the need for main memory access under demanding workloads, resulting in an overall enhancement to system performance. Cache memory is two-way interleaved 200 MHz DDR memory and is faster than the main memory because it is directly connected to the Cache and Scalability Controller and does not have additional latency associated with the large fan-out necessary to support the 28 DIMM slots. Since the data interface to the controller is 400 MHz, peak bandwidth for the XceL4 cache is 6.4 GBps. The XceL4 Accelerator Cache has been designed with commercial workloads in mind that tend to have high cache hit rates. This effectively boosts performance and compensates in part for the 3.2 GBps bandwidth between the Cache and Scalability Controller and Memory Controller. 12 IBM xSeries 455 Planning and Installation Guide Eserver

Section	Page
Front cover	1
Contents	5
Notices	9
Trademarks	10
Preface	11
The team that wrote this redbook	11
Become a published author	13
Comments welcome	14
Chapter 1. Technical description	15
1.1 Features	16
1.1.1 Comparing the x455 with the x450	16
1.1.2 Features not supported	17
1.2 The x455 base models	18
1.2.1 Front and rear views	18
1.3 System assembly	20
1.4 IBM XA-64 chipset	21
1.4.1 The processor-board assembly	23
1.4.2 The memory-board assembly	27
1.4.3 PCI-X board assembly	31
1.5 Remote Supervisor Adapter	33
1.6 RXE-100 Expansion Enclosure	35
1.7 Multinode scalable partitions	36
1.7.1 RXE-100 connectivity	38
1.7.2 Multinode configuration	39
1.7.3 Integrated I/O function support	40
1.7.4 Error recovery	40
1.8 Redundancy	41
1.9 Light path diagnostics	41
1.10 Extensible Firmware Interface	43
1.10.1 GUID Partition Table disk	45
1.10.2 EFI System Partition	47
1.10.3 EFI and the reduced-legacy concept	48
1.11 Operating system support	49
1.12 Enterprise X-Architecture	49
1.12.1 NUMA architecture	50
Chapter 2. Positioning	53
2.1 Migrating to a 64-bit platform	54
2.2 Scalable system partitioning	55
2.2.1 RXE-100 Expansion Enclosure	56
2.3 Operating system support	56
2.4 Server consolidation	57
2.5 ServerProven®	58
2.6 IBM Datacenter Solution Program	59
2.7 Application solutions	60
2.7.1 Database applications	60
2.7.2 Business logic	62
2.7.3 e-Business and security transactions	64
2.7.4 In-house developed compute-intensive applications	65
2.7.5 Science and technology industries	65
2.8 Why choose x455	66
Chapter 3. Planning	69
3.1 System hardware	70
3.1.1 Processors	70
3.1.2 Memory	71
3.1.3 PCI-X slot configuration	75
3.1.4 Broadcom Gigabit Ethernet controller	78
3.2 Cabling and connectivity	79
3.2.1 SMP Expansion connectivity	81
3.2.2 Remote Expansion Enclosure connectivity	84
3.2.3 Remote Supervisor Adapter connectivity	90
3.2.4 Serial connectivity	92
3.3 Storage considerations	93
3.3.1 xSeries storage solutions	93
3.3.2 Tape backup	98
3.4 Rack installation	99
3.5 Power considerations	101
3.6 Operating system support	101
3.6.1 Clustering	102
3.7 IBM Director support	103
3.8 Solution Assurance Review	104
3.8.1 Trigger Tool	104
3.8.2 Electronic Solution Assurance Review (eSAR)	104
Chapter 4. Installation	105
4.1 Using The Extensible Firmware Interface	106
4.1.1 EFI Firmware Boot Manager	107
4.1.2 The EFI shell	109
4.1.3 Driver Setup	117
4.1.4 Flash update	126
4.1.5 Configuration/Setup utility	132
4.1.6 Diagnostic utility	135
4.1.7 Boot Option Maintenance	136
4.2 Configuring scalable partitions	145
4.2.1 Creating a scalable partition	145
4.2.2 Booting a scalable partition	148
4.2.3 Multiple Monitors	149
4.2.4 Deleting a scalable partition	150
4.3 Installing Windows Server 2003	150
4.3.1 Important information	150
4.3.2 Preparing to install	152
4.3.3 Installation	153
4.3.4 Post-setup phase	158
4.4 Installing Linux	165
4.4.1 Linux IA-64 kernel overview	166
4.4.2 Choosing a Linux distribution	167
4.4.3 Installing SUSE LINUX Enterprise Server 8.0	170
4.4.4 Installing Red Hat Enterprise Linux AS	174
4.4.5 Linux boot process	176
4.4.6 Information about the installed system	177
4.4.7 Using the serial port for the Linux console	185
4.4.8 RXE-100 Expansion Enclosure	186
4.4.9 Upgrading drivers	187
Chapter 5. Management	189
5.1 IBM Director	190
5.1.1 Scalable Systems Manager	191
5.2 The Remote Supervisor Adapter	191
5.2.1 Connecting via a Web browser	193
5.2.2 Connecting via the ASM interconnect	198
5.2.3 Installing the device driver	199
5.2.4 Configuring the remote control password	200
5.3 Management using the Remote Supervisor Adapter	201
5.3.1 Configuring which alerts to monitor	202
5.3.2 Configuring SNMP	204
5.3.3 Sending alerts directly to IBM Director	205
5.3.4 Creating a test event action plan in IBM Director	207
5.4 Windows System Resource Manager	210
5.4.1 WSRM description	211
5.4.2 WSRM features	212
5.4.3 WSRM in the x455	213
Abbreviations and acronyms	215
Related publications	217
IBM Redbooks	217
Other publications	217
Online resources	218
How to get IBM Redbooks	222
Help from IBM	222
Index	223

Match case Limit results 1 per page

IBM

Eserver

xSeries 455 Planning and Installation Guide

Specifically, in today's 32-bit processors, much of the instruction scheduling

(the order in which computing instructions are executed) is done on the chip

itself, leading to a great deal of overhead and slowing down overall processor

performance. Moreover, today's processors are plagued by instruction flow

problems since the processor often has to stop what it is doing and

reconstruct the instruction flow due to inherent inefficiencies in instruction

handling.

EPIC makes the instruction scheduling more intelligent and handles much of

the scheduling off-chip, in the compiler program, before feeding “parallelized”

instructions to the Itanium 2 processor for execution. The parallelized

instructions allow the chip to process a number of instructions simultaneously,

increasing performance.

The Itanium 2 architecture is based on EPIC technology and has the following

features:

–

Provides faster online transaction processing

–

Has the capability to execute multiple instructions simultaneously

–

Enables faster calculations and data analysis

–

Allows for faster storage and movement of large models (CAD, CAE)

–

Speeds up simulation and rendering times

For more information about the features of the Itanium 2 processor, go to:

http://www.intel.com/design/itanium2

IBM XceL4 Accelerator Cache

Integrated into the processor-board assembly is 64 MB of Level 4 cache, which is

shown in Figure 1-4 on page 8. This XceL4 Server Accelerator Cache provides

the necessary extra level of cache to maximize CPU throughput by reducing the

need for main memory access under demanding workloads, resulting in an

overall enhancement to system performance.

Cache memory is two-way interleaved 200 MHz DDR memory and is faster than

the main memory because it is directly connected to the Cache and Scalability

Controller and does not have additional latency associated with the large fan-out

necessary to support the 28 DIMM slots. Since the data interface to the controller

is 400 MHz, peak bandwidth for the XceL4 cache is 6.4 GBps.

The XceL4 Accelerator Cache has been designed with commercial workloads in

mind that tend to have high cache hit rates. This effectively boosts performance

and compensates in part for the 3.2 GBps bandwidth between the Cache and

Scalability Controller and Memory Controller.