Brother International MFC-P2000 Service Manual - Page 23

(5) Timers The following timers are incorporated: Timer 1 16-bit timer Timer 2 10-bit timer Timer 3 Watch-dog timer (6) FIFO A 5,120-bit FIFO is incorporated. Data for one raster scan is transferred from the RAM to the FIFO by DMA transmission and is output as serial video data. The data cycle rate is 10.22 MHz. (7) CDCC parallel I/O There are two modes in this unit. One is the CPU receiving mode and the other is the DMA receiving mode. In the CPU receiving mode the CPU receives the command data from the PC, and after the CPU is switched to the DMA mode, it receives the image data and writes to the DRAM directly. CPU Receive Mode STROBE BUSY ACK 90 µsec 0.5 µsec DMA Receive Mode STROBE BUSY ACK 1.5 µsec 0.5 µsec BUSY goes HIGH at the falling edge of STROBE. The data (8 bits) from the PC is latched in the data buffer at the rising edge of STROBE. The pulse width of ACK differs according to the speed MODE as shown above. BUSY goes LOW at the rising edge of ACK. This supports the IEEE1284 data transfer with the following modes. Nibble mode Byte mode (8) Data expansion This circuit expands the compressed image data received from the PC, and writes the bit map data to the FIFO. (9) Software support Supports 16 x 16 rotation, bit expansion and bit search. II-4