HP Integrity rx8620 Installation Guide, Sixth Edition - HP Integrity rx8620 Se - Page 16

Introduction Detailed HP Integrity rx8620 Server Description Figure 1-6 shows a simplified view of the memory subsystem. It consists of two independent access paths, each path having its own address bus, control bus, data bus, and DIMMs. In practice, the CC runs the two paths 180 degrees out of phase with respect to each other to facilitate pipelining in the CC. Address and control signals are fanned out through register ports to the synchronous dynamic random access memory (SDRAM) on the DIMMs. The memory subsystem is composed of four independent quadrants. Each quadrant has its own memory data bus connecting from the cell controller to the two buffers for the memory quadrant. Each quadrant also has two memory control buses; one for each buffer. Figure 1-6 Memory Subsystem QUAD 1 QUAD 3 DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM PDH Riser Board DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM QUAD 0 To Quad 2 Address/Controller Buffers To Quad 3 Address/Controller Buffers To Quad 1 Address/Controller Buffers To Quad 0 Address/Controller Buffers QUAD 2 DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM Front Side Bus 1 CPU 2 CPU 3 Cell Controller DIMM DIMM Address/ Buffer Controller Buffer Buffer DIMM DIMM Front Side Bus 0 CPU 1 CPU 0 16 Chapter 1