Intel D845PEBT2 Product Specification - Page 123

Error Messages and Beep Codes, Description of POST Operation

Get Intel D845PEBT2 PDF manuals and user guides View all Intel D845PEBT2 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 123 highlights

Error Messages and Beep Codes Table 92. Runtime Code Uncompressed in F000 Shadow RAM (continued) Code 40 42 43 44 45 46 47 48 49 4B 4C 4D 4E 4F 50 51 52 53 54 57 58 59 60 62 65 66 7F 80 81 82 83 Description of POST Operation To prepare the descriptor tables. To enter in virtual mode for memory test. To enable interrupts for diagnostics mode. To initialize data to check memory wrap around at 0:0. Data initialized. Going to check for memory wrap around at 0:0 and finding the total system memory size. Memory wrap around test done. Memory size calculation over. About to go for writing patterns to test memory. Pattern to be tested written in extended memory. Going to write patterns in base 640k memory. Patterns written in base memory. Going to find out amount of memory below 1M memory. Amount of memory below 1M found and verified. Going to find out amount of memory above 1M memory. Amount of memory above 1M found and verified. Check for soft reset and going to clear memory below 1M for soft reset. (If power on, go to check point # 4Eh). Memory below 1M cleared. (SOFT RESET) Going to clear memory above 1M. Memory above 1M cleared. (SOFT RESET) Going to save the memory size. (Go to check point # 52h). Memory test started. (NOT SOFT RESET) About to display the first 64k memory size. Memory size display started. This will be updated during memory test. Going for sequential and random memory test. Memory testing/initialization below 1M complete. Going to adjust displayed memory size for relocation/shadow. Memory size display adjusted due to relocation/ shadow. Memory test above 1M to follow. Memory testing/initialization above 1M complete. Going to save memory size information. Memory size information is saved. CPU registers are saved. Going to enter in real mode. Shutdown successful, CPU in real mode. Going to disable gate A20 line and disable parity/NMI. A20 address line, parity/NMI disable successful. Going to adjust memory size depending on relocation/shadow. Memory size adjusted for relocation/shadow. Going to clear Hit message. Hit message cleared. message displayed. About to start DMA and interrupt controller test. DMA page register test passed. To do DMA#1 base register test. DMA#1 base register test passed. To do DMA#2 base register test. DMA#2 base register test passed. To program DMA unit 1 and 2. DMA unit 1 and 2 programming over. To initialize 8259 interrupt controller. Extended NMI sources enabling is in progress. Keyboard test started. Clearing output buffer, checking for stuck key, to issue keyboard reset command. Keyboard reset error/stuck key found. To issue keyboard controller interface test command. Keyboard controller interface test over. To write command byte and init circular buffer. Command byte written, global data init done. To check for lock-key. continued 123

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
  • 128
Error Messages and Beep Codes
123
Table 92.
Runtime Code Uncompressed in F000 Shadow RAM
(continued)
Code
Description of POST Operation
40
To prepare the descriptor tables.
42
To enter in virtual mode for memory test.
43
To enable interrupts for diagnostics mode.
44
To initialize data to check memory wrap around at 0:0.
45
Data initialized.
Going to check for memory wrap around at 0:0 and finding the total system
memory size.
46
Memory wrap around test done.
Memory size calculation over.
About to go for writing patterns to
test memory.
47
Pattern to be tested written in extended memory.
Going to write patterns in base 640k memory.
48
Patterns written in base memory.
Going to find out amount of memory below 1M memory.
49
Amount of memory below 1M found and verified.
Going to find out amount of memory above
1M memory.
4B
Amount of memory above 1M found and verified.
Check for soft reset and going to clear memory
below 1M for soft reset. (If power on, go to check point # 4Eh).
4C
Memory below 1M cleared.
(SOFT RESET) Going to clear memory above 1M.
4D
Memory above 1M cleared. (SOFT RESET) Going to save the memory size. (Go to check
point # 52h).
4E
Memory test started.
(NOT SOFT RESET) About to display the first 64k memory size.
4F
Memory size display started.
This will be updated during memory test.
Going for sequential and
random memory test.
50
Memory testing/initialization below 1M complete.
Going to adjust displayed memory size for
relocation/shadow.
51
Memory size display adjusted due to relocation/ shadow.
Memory test above 1M to follow.
52
Memory testing/initialization above 1M complete.
Going to save memory size information.
53
Memory size information is saved.
CPU registers are saved.
Going to enter in real mode.
54
Shutdown successful, CPU in real mode.
Going to disable gate A20 line and disable parity/NMI.
57
A20 address line, parity/NMI disable successful.
Going to adjust memory size depending on
relocation/shadow.
58
Memory size adjusted for relocation/shadow.
Going to clear Hit <DEL> message.
59
Hit <DEL> message cleared.
<WAIT...> message displayed.
About to start DMA and interrupt
controller test.
60
DMA page register test passed.
To do DMA#1 base register test.
62
DMA#1 base register test passed.
To do DMA#2 base register test.
65
DMA#2 base register test passed.
To program DMA unit 1 and 2.
66
DMA unit 1 and 2 programming over.
To initialize 8259 interrupt controller.
7F
Extended NMI sources enabling is in progress.
80
Keyboard test started.
Clearing output buffer, checking for stuck key, to issue keyboard reset
command.
81
Keyboard reset error/stuck key found.
To issue keyboard controller interface test command.
82
Keyboard controller interface test over.
To write command byte and init circular buffer.
83
Command byte written, global data init done.
To check for lock-key.
continued