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Fixed I/O Map

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Intel Desktop Board D845PEBT2 Technical Product Specification 2.3 Fixed I/O Map Table 11. I/O Map Address (hex) Size Description 0000 - 00FF 256 bytes Used by the Desktop Board D845PEBT2. Refer to the ICH4 data sheet for dynamic addressing information 0170 - 0177 8 bytes Secondary IDE channel 01F0 - 01F7 8 bytes Primary IDE channel 0228 - 022F (Note 1) 0278 - 027F (Note 1) 02E8 - 02EF (Note 1) 02F8 - 02FF (Note 1) 8 bytes 8 bytes 8 bytes 8 bytes LPT3 LPT2 COM4/video (8514A) COM2 0376 0377, bits 6:0 0378 - 037F 03B0 - 03BB 03C0 - 03DF 03E8 - 03EF 03F0 - 03F5 1 byte 7 bits 8 bytes 12 bytes 32 bytes 8 bytes 6 bytes Secondary IDE channel command port Secondary IDE channel status port LPT1 Intel 82845PE MCH Intel 82845PE MCH COM3 Diskette channel 1 03F6 1 byte Primary IDE channel command port 03F8 - 03FF 8 bytes COM1 04D0 - 04D1 2 bytes Edge/level triggered PIC LPTn + 400 0CF8 - 0CFB (Note 2) 0CF9 (Note 3) 0CFC - 0CFF FFA0 - FFA7 FFA8 - FFAF 8 bytes 4 bytes 1 byte 4 bytes 8 bytes 8 bytes ECP port, LPTn base address + 400h PCI configuration address register Turbo and reset control register PCI configuration data register Primary bus master IDE registers Secondary bus master IDE registers Notes: 1. Default, but can be changed to another address range 2. Dword access only 3. Byte access only For information about ICH4 addressing Refer to Section 1.2, page 16 46

Section	Page
Intel® Desktop Board D845PEBT2 Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Notes, Cautions, and Warnings	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 Overview	12
1.1.1 Feature Summary	12
1.1.2 Manufacturing Options	13
1.1.3 Board Layout	14
1.1.4 Block Diagram	15
1.2 Online Support	16
1.3 Operating System Support	16
1.4 Design Specifications	17
1.5 Processor	20
1.6 System Memory	21
1.7 Intel® 845PE Chipset	23
1.7.1 AGP	24
1.7.2 USB	24
1.7.3 IDE Support	25
1.7.4 Real-Time Clock, CMOS SRAM, and Battery	26
1.7.5 Intel® 82802AB Firmware Hub (FWH)	26
1.8 IDE RAID Controller (Optional)	27
1.9 Serial ATA Controller (Optional)	27
1.10 I/O Controller	28
1.10.1 Serial Ports	28
1.10.2 Parallel Port	28
1.10.3 Diskette Drive Controller	28
1.10.4 Keyboard and Mouse Interface	29
1.11 IEEE 1394a-2000 Controller (Optional)	29
1.12 Audio Subsystem	30
1.12.1 6-Channel Audio Subsystem (Optional)	30
1.12.2 2-Channel Audio Subsystem (Optional)	31
1.12.3 Audio Connectors	32
1.12.4 Audio Subsystem Software	32
1.13 LAN Subsystem	33
1.13.1 Intel® 82562ET Physical Layer Interface Device	33
1.13.2 RJ-45 LAN Connector with Integrated LEDs	33
1.13.3 LAN Subsystem Software	34
1.14 CNR (Optional)	34
1.15 Hardware Management Subsystem	35
1.15.2 Fan Monitoring	36
1.15.3 Chassis Intrusion and Detection	37
1.16 Power Management	37
1.16.1 ACPI	38
1.16.2 Hardware Support	40
2 Technical Reference	45
2.1 Introduction	45
2.2 Memory Map	45
2.3 Fixed I/O Map	46
2.4 DMA Channels	47
2.5 PCI Configuration Space Map	47
2.6 Interrupts	48
2.7 PCI Interrupt Routing Map	49
2.8 Connectors	51
2.8.1 Back Panel Connectors	52
2.8.2 Internal I/O Connectors	56
2.8.3 External I/O Connectors	68
2.9 Jumper Blocks	72
2.9.1 Front Panel Audio Connector/Jumper Block	72
2.9.2 BIOS Setup Configuration Jumper Block	73
2.10 Mechanical Considerations	74
2.10.1 D845PEBT2 Form Factor	74
2.10.2 I/O Shield	76
2.11 Electrical Considerations	79
2.11.1 Power Consumption	79
2.11.2 Add-in Board Considerations	79
2.11.3 Standby Current Requirements	80
2.11.4 Fan Connector Current Capability	81
2.11.5 Power Supply Considerations	82
2.12 Thermal Considerations	83
2.13 Reliability	85
2.14 Environmental	85
2.15 Regulatory Compliance	86
2.15.1 Safety Regulations	86
2.15.2 EMC Regulations	86
2.15.3 Product Certification Markings (Board Level)	87
3 Overview of BIOS Features	89
3.1 Introduction	89
3.2 BIOS Flash Memory Organization	90
3.3 PCI Autoconfiguration	90
3.4 System Management BIOS (SMBIOS)	90
3.5 Legacy USB Support	91
3.6 BIOS Updates	91
3.6.1 Language Support	92
3.6.2 Custom Splash Screen	92
3.7 Recovering BIOS Data	92
3.8 Boot Options	93
3.8.1 CD-ROM Boot	93
3.8.2 Network Boot	93
3.8.3 Booting Without Attached Devices	93
3.9 Changing the Default Boot Device During POST	94
3.10 Fast Booting Systems with Intel® Rapid BIOS Boot	94
3.10.1 Peripheral Selection and Configuration	94
3.10.2 Intel Rapid BIOS Boot	95
3.11 BIOS Security Features	96
4 BIOS Setup Program	97
4.1 Introduction	97
4.2 Maintenance Menu	98
4.3 Main Menu	99
4.4 Advanced Menu	100
4.4.1 PCI Configuration Submenu	101
4.4.2 Boot Configuration Submenu	102
4.4.3 Peripheral Configuration Submenu	103
4.4.4 IDE Configuration Submenu	105
4.4.5 Diskette Configuration Submenu	107
4.4.6 Event Log Configuration Submenu	108
4.4.7 Video Configuration Submenu	109
4.4.8 USB Configuration Submenu	110
4.4.9 Chipset Configuration Submenu	111
4.4.10 Fan Control Configuration Submenu	112
4.5 Security Menu	113
4.6 Power Menu	114
4.6.1 ACPI Submenu	114
4.7 Boot Menu	115
4.7.1 Boot Device Priority Submenu	116
4.7.2 Hard Disk Drives Submenu	117
4.7.3 Removable Devices Submenu	117
4.7.4 ATAPI CD-ROM Drives Submenu	118
4.8 Exit Menu	118
5 Error Messages and Beep Codes	119
5.1 BIOS Error Messages	119
5.2 Port 80h POST Codes	121
5.3 Bus Initialization Checkpoints	125
5.4 Speaker	126

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Intel Desktop Board D845PEBT2 Technical Product Specification

2.3 Fixed I/O Map

Table 11.

I/O Map

Address (hex)

Size

Description

0000 - 00FF

256 bytes

Used by the Desktop Board D845PEBT2.

Refer to the

ICH4 data sheet for dynamic addressing information

0170 - 0177

8 bytes

Secondary IDE channel

01F0 - 01F7

8 bytes

Primary IDE channel

0228 - 022F

(Note 1)

8 bytes

LPT3

0278 - 027F

(Note 1)

8 bytes

LPT2

02E8 - 02EF

(Note 1)

8 bytes

COM4/video (8514A)

02F8 - 02FF

(Note 1)

8 bytes

COM2

0376

1 byte

Secondary IDE channel command port

0377, bits 6:0

7 bits

Secondary IDE channel status port

0378 - 037F

8 bytes

LPT1

03B0 - 03BB

12 bytes

Intel 82845PE MCH

03C0 - 03DF

32 bytes

Intel 82845PE MCH

03E8 - 03EF

8 bytes

COM3

03F0 - 03F5

6 bytes

Diskette channel 1

03F6

1 byte

Primary IDE channel command port

03F8 - 03FF

8 bytes

COM1

04D0 - 04D1

2 bytes

Edge/level triggered PIC

LPTn + 400

8 bytes

ECP port, LPTn base address + 400h

0CF8 - 0CFB

(Note 2)

4 bytes

PCI configuration address register

0CF9

(Note 3)

1 byte

Turbo and reset control register

0CFC - 0CFF

4 bytes

PCI configuration data register

FFA0 - FFA7

8 bytes

Primary bus master IDE registers

FFA8 - FFAF

8 bytes

Secondary bus master IDE registers

Notes:

Default, but can be changed to another address range

Dword access only

Byte access only

For information about

Refer to

ICH4 addressing

Section 1.2, page 16