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Table 37., PCI Bus Connectors

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Technical Reference Table 37. PCI Bus Connectors Pin Signal Name Pin Signal Name Pin Signal Name A1 Ground (TRST#)* B1 -12 V A32 AD16 A2 +12 V B2 Ground (TCK)* A33 +3.3 V A3 +5 V (TMS)* B3 Ground A34 FRAME# A4 +5 V (TDI)* B4 Not connected (TDO)* A35 Ground A5 +5 V B5 +5 V A36 TRDY# A6 INTA# B6 +5 V A37 Ground A7 INTC# B7 INTB# A38 STOP# A8 +5 V B8 INTD# A39 +3.3 V A9 Reserved B9 Not connected (PRSNT1#)* A40 Reserved ** Pin Signal Name B32 AD17 B33 C/BE2# B34 Ground B35 IRDY# B36 +3.3 V B37 DEVSEL# B38 Ground B39 LOCK# B40 PERR# A10 +5 V (I/O) B10 Reserved A41 Reserved *** B41 +3.3 V A11 Reserved B11 Not connected (PRSNT2#)* A42 Ground B42 SERR# A12 Ground B12 Ground A43 PAR B43 +3.3 V A13 Ground B13 Ground A44 AD15 B44 C/BE1# A14 +3.3 V aux B14 Reserved A45 +3.3 V B45 AD14 A15 RST# B15 Ground A46 AD13 B46 Ground A16 +5 V (I/O) B16 CLK A47 AD11 B47 AD12 A17 GNT# B17 Ground A48 Ground B48 AD10 A18 Ground B18 REQ# A49 AD09 B49 Ground A19 PME# B19 +5 V (I/O) A50 Key B50 Key A20 AD30 B20 AD31 A51 Key B51 Key A21 +3.3 V B21 AD29 A52 C/BE0# B52 AD08 A22 AD28 B22 Ground A53 +3.3 V B53 AD07 A23 AD26 B23 AD27 A54 AD06 B54 +3.3 V A24 Ground B24 AD25 A55 AD04 B55 AD05 A25 AD24 B25 +3.3 V A56 Ground B56 AD03 A26 IDSEL B26 C/BE3# A57 AD02 B57 Ground A27 +3.3 V A28 AD22 A29 AD20 A30 Ground A31 AD18 B27 AD23 B28 Ground B29 AD21 B30 AD19 B31 +3.3 V A58 AD00 A59 +5 V (I/O) A60 REQ64# A61 +5 V A62 +5 V B58 AD01 B59 +5 V (I/O) B60 ACK64# B61 +5 V B62 +5 V * These signals (in parentheses) are optional in the PCI specification and are not currently implemented. ** On PCI bus connector 1 or 2 (see section 2.8.2.1 on page 57), this pin is connected to the SMBus clock line. *** On PCI bus connector 1 or 2 (see section 2.8.2.1 on page 57), this pin is connected to the SMBus data line. 63

Section	Page
Intel® Desktop Board D845PEBT2 Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Notes, Cautions, and Warnings	3
Other Common Notation	4
Contents	5
1 Product Description	11
1.1 Overview	12
1.1.1 Feature Summary	12
1.1.2 Manufacturing Options	13
1.1.3 Board Layout	14
1.1.4 Block Diagram	15
1.2 Online Support	16
1.3 Operating System Support	16
1.4 Design Specifications	17
1.5 Processor	20
1.6 System Memory	21
1.7 Intel® 845PE Chipset	23
1.7.1 AGP	24
1.7.2 USB	24
1.7.3 IDE Support	25
1.7.4 Real-Time Clock, CMOS SRAM, and Battery	26
1.7.5 Intel® 82802AB Firmware Hub (FWH)	26
1.8 IDE RAID Controller (Optional)	27
1.9 Serial ATA Controller (Optional)	27
1.10 I/O Controller	28
1.10.1 Serial Ports	28
1.10.2 Parallel Port	28
1.10.3 Diskette Drive Controller	28
1.10.4 Keyboard and Mouse Interface	29
1.11 IEEE 1394a-2000 Controller (Optional)	29
1.12 Audio Subsystem	30
1.12.1 6-Channel Audio Subsystem (Optional)	30
1.12.2 2-Channel Audio Subsystem (Optional)	31
1.12.3 Audio Connectors	32
1.12.4 Audio Subsystem Software	32
1.13 LAN Subsystem	33
1.13.1 Intel® 82562ET Physical Layer Interface Device	33
1.13.2 RJ-45 LAN Connector with Integrated LEDs	33
1.13.3 LAN Subsystem Software	34
1.14 CNR (Optional)	34
1.15 Hardware Management Subsystem	35
1.15.2 Fan Monitoring	36
1.15.3 Chassis Intrusion and Detection	37
1.16 Power Management	37
1.16.1 ACPI	38
1.16.2 Hardware Support	40
2 Technical Reference	45
2.1 Introduction	45
2.2 Memory Map	45
2.3 Fixed I/O Map	46
2.4 DMA Channels	47
2.5 PCI Configuration Space Map	47
2.6 Interrupts	48
2.7 PCI Interrupt Routing Map	49
2.8 Connectors	51
2.8.1 Back Panel Connectors	52
2.8.2 Internal I/O Connectors	56
2.8.3 External I/O Connectors	68
2.9 Jumper Blocks	72
2.9.1 Front Panel Audio Connector/Jumper Block	72
2.9.2 BIOS Setup Configuration Jumper Block	73
2.10 Mechanical Considerations	74
2.10.1 D845PEBT2 Form Factor	74
2.10.2 I/O Shield	76
2.11 Electrical Considerations	79
2.11.1 Power Consumption	79
2.11.2 Add-in Board Considerations	79
2.11.3 Standby Current Requirements	80
2.11.4 Fan Connector Current Capability	81
2.11.5 Power Supply Considerations	82
2.12 Thermal Considerations	83
2.13 Reliability	85
2.14 Environmental	85
2.15 Regulatory Compliance	86
2.15.1 Safety Regulations	86
2.15.2 EMC Regulations	86
2.15.3 Product Certification Markings (Board Level)	87
3 Overview of BIOS Features	89
3.1 Introduction	89
3.2 BIOS Flash Memory Organization	90
3.3 PCI Autoconfiguration	90
3.4 System Management BIOS (SMBIOS)	90
3.5 Legacy USB Support	91
3.6 BIOS Updates	91
3.6.1 Language Support	92
3.6.2 Custom Splash Screen	92
3.7 Recovering BIOS Data	92
3.8 Boot Options	93
3.8.1 CD-ROM Boot	93
3.8.2 Network Boot	93
3.8.3 Booting Without Attached Devices	93
3.9 Changing the Default Boot Device During POST	94
3.10 Fast Booting Systems with Intel® Rapid BIOS Boot	94
3.10.1 Peripheral Selection and Configuration	94
3.10.2 Intel Rapid BIOS Boot	95
3.11 BIOS Security Features	96
4 BIOS Setup Program	97
4.1 Introduction	97
4.2 Maintenance Menu	98
4.3 Main Menu	99
4.4 Advanced Menu	100
4.4.1 PCI Configuration Submenu	101
4.4.2 Boot Configuration Submenu	102
4.4.3 Peripheral Configuration Submenu	103
4.4.4 IDE Configuration Submenu	105
4.4.5 Diskette Configuration Submenu	107
4.4.6 Event Log Configuration Submenu	108
4.4.7 Video Configuration Submenu	109
4.4.8 USB Configuration Submenu	110
4.4.9 Chipset Configuration Submenu	111
4.4.10 Fan Control Configuration Submenu	112
4.5 Security Menu	113
4.6 Power Menu	114
4.6.1 ACPI Submenu	114
4.7 Boot Menu	115
4.7.1 Boot Device Priority Submenu	116
4.7.2 Hard Disk Drives Submenu	117
4.7.3 Removable Devices Submenu	117
4.7.4 ATAPI CD-ROM Drives Submenu	118
4.8 Exit Menu	118
5 Error Messages and Beep Codes	119
5.1 BIOS Error Messages	119
5.2 Port 80h POST Codes	121
5.3 Bus Initialization Checkpoints	125
5.4 Speaker	126

Match case Limit results 1 per page

Technical Reference

Table 37.

PCI Bus Connectors

Signal Name

Ground (TRST#)*

-12 V

A32

AD16

B32

AD17

+12 V

Ground (TCK)*

A33

+3.3 V

B33

C/BE2#

+5 V (TMS)*

Ground

A34

FRAME#

B34

Ground

+5 V (TDI)*

Not connected (TDO)*

A35

Ground

B35

IRDY#

+5 V

A36

TRDY#

B36

+3.3 V

INTA#

+5 V

A37

Ground

B37

DEVSEL#

INTC#

INTB#

A38

STOP#

B38

Ground

+5 V

INTD#

A39

+3.3 V

B39

LOCK#

Reserved

Not connected

(PRSNT1#)*

A40

Reserved **

B40

PERR#

A10

+5 V (I/O)

B10

Reserved

A41

Reserved ***

B41

+3.3 V

A11

Reserved

B11

Not connected

(PRSNT2#)*

A42

Ground

B42

SERR#

A12

Ground

B12

Ground

A43

PAR

B43

+3.3 V

A13

Ground

B13

Ground

A44

AD15

B44

C/BE1#

A14

+3.3 V aux

B14

Reserved

A45

+3.3 V

B45

AD14

A15

RST#

B15

Ground

A46

AD13

B46

Ground

A16

+5 V (I/O)

B16

CLK

A47

AD11

B47

AD12

A17

GNT#

B17

Ground

A48

Ground

B48

AD10

A18

Ground

B18

REQ#

A49

AD09

B49

Ground

A19

PME#

B19

+5 V (I/O)

A50

Key

B50

Key

A20

AD30

B20

AD31

A51

Key

B51

Key

A21

+3.3 V

B21

AD29

A52

C/BE0#

B52

AD08

A22

AD28

B22

Ground

A53

+3.3 V

B53

AD07

A23

AD26

B23

AD27

A54

AD06

B54

+3.3 V

A24

Ground

B24

AD25

A55

AD04

B55

AD05

A25

AD24

B25

+3.3 V

A56

Ground

B56

AD03

A26

IDSEL

B26

C/BE3#

A57

AD02

B57

Ground

A27

+3.3 V

B27

AD23

A58

AD00

B58

AD01

A28

AD22

B28

Ground

A59

+5 V (I/O)

B59

+5 V (I/O)

A29

AD20

B29

AD21

A60

REQ64#

B60

ACK64#

A30

Ground

B30

AD19

A61

+5 V

B61

+5 V

A31

AD18

B31

+3.3 V

A62

+5 V

B62

+5 V

These signals (in parentheses) are optional in the PCI specification and are not currently implemented.

On PCI bus connector 1 or 2 (see section 2.8.2.1 on page 57), this pin is connected to the SMBus clock line.

***

On PCI bus connector 1 or 2 (see section 2.8.2.1 on page 57), this pin is connected to the SMBus data line.