Hitachi C4K60 Specifications - Page 130

Interface Signal Timing, 1. Data Transfer Timing

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8.0 Interface Signal Timing 8.1. Data Transfer Timing Figures 8-1, 8-2, and 8-3 show the timing for asserting interface signals for transferring 16-bit and 8-bit data. Figure 8.1 PIO Data Transfer Timing (Mode 4) Addr Valid *1 t1 DIOR-/DIOW- Write Data Valid *2 Read Data Valid *2 t0 t2 t7 t2i t3 t4 t5 t6 t6Z *1 Device Address consists of signals CS0-, CS1-, and DA2-0 *2 Data consists of DD0-15(16 bit) or DD0-7(8 bit) SYMBOL Description t0 Cycle Time t1 Address Valid to DIOR-/DIOW- Setup t2 DIOR-/DIOW- Pulse Width t2i DIOR-/DIOW- Recovery t3 DIOW- Data Setup t4 DIOW- Data Hold t5 DIOR- Data Setup t6 DIOR- Data Hold t6Z DIOR- Data tristate t7 DIOR-/DIOW- to Address Valid Hold MIN(ns) 120 25 70 25 20 10 20 5 10 MAX(ns) 30 K6610170 Rev.2 Dec 22, 2004 - 130 -

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K6610170
Rev.2
Dec 22, 2004
- 130 -
8.0 Interface Signal Timing
8.1. Data Transfer Timing
Figures 8-1, 8-2, and 8-3 show the timing for asserting interface signals for transferring 16-bit and
8-bit data.
Figure 8.1 PIO Data Transfer Timing (Mode 4)
*1
Device Address consists of signals CS0-, CS1-, and DA2-0
*2
Data consists of DD0-15(16 bit) or DD0-7(8 bit)
SYMBOL
Description
MIN(ns)
MAX(ns)
t
0
Cycle Time
120
t
1
Address Valid to DIOR-/DIOW- Setup
25
t
2
DIOR-/DIOW- Pulse Width
70
t
2
i
DIOR-/DIOW- Recovery
25
t
3
DIOW- Data Setup
20
t
4
DIOW- Data Hold
10
t
5
DIOR- Data Setup
20
t
6
DIOR- Data Hold
5
t
6Z
DIOR- Data tristate
30
t
7
DIOR-/DIOW- to Address Valid Hold
10
t
1
t
7
t
2
t
3
t
5
t
4
t
6
Addr Valid *1
DIOR-/DIOW-
Write Data Valid *2
Read Data Valid *2
t
0
t
2i
t
6Z