Hitachi C4K60 Specifications - Page 66

Word Table 7.8 IDENTIFY DEVICE information(Continued) Description 50 Capabilities bit 15 0 (fixed) bit 14 1 (fixed) bit 13 - 1 0 = Reserved bit 0 1 = minimum value of standby timer is device specific 51 Bit 15 - 8 PIO data transfer cycle timing mode Bit 7 - 0 Vendor Specific 52 Obsolete 53 Field validity bit 15 - 3 0 = Reserved bit 2 1 = The field reported in word 88 is valid bit 1 1 = The fields reported words 64-70 are valid bit 0 1 = The fields reported words 54-58 are valid 54 Number of current cylinders 55 Number of current heads 56 Number of current sectors per track 57-58 Current capacity in sectors 59 Multiple sector setting bit 15-9 0 = Reserved bit 8 1 = Multiple sector setting is valid bit 7 - 0 Current setting for number of sectors that can be transferred per interrupt on R/W MULTIPLE command 60-61 Total addressable LBA 62 63 64 65 66 67 68 69-74 75 76-79 Obsolete Multi-word DMA transfer bit 15 - 8 Multi-word DMA transfer mode active bit 7 - 0 Multi-word DMA transfer mode supported Flow control PIO transfer Modes supported bit 15 - 2 0 = Reserved bit 1 1 = PIO Mode 4 supported bit 0 1 = PIO Mode 3 supported Minimum Multi-word DMA Transfer Cycle Time Per Word(ns) Manufacturer's Recommended Multi-word DMA Cycle Time(ns) Minimum PIO Transfer Cycle Time without Flow Control(ns) Minimum PIO Transfer Cycle Time with IORDY(ns) Reserved Queue Depth bit 15 - 5 0 = Reserved bit 4 - 0 Maximum queue depth Reserved Value (HEX.) 4000h 0200h 0000h 0007h See Table 7.9 0000h 0003h 0078h 0078h 00F0h 0078h 0000h 0000h 0000h K6610170 Rev.2 Dec 22, 2004 - 66 -