Hitachi C4K60 Specifications - Page 56

Table 7.5 DEVICE CONFIGURATION IDENTIFY Data Structure Word 0 1 2 3 - 6 7 8 - 254 255 Description Data Structure Revision Multiword DMA modes supported bit 15 - 3 0 = Reserved bit 2 1 = Multiword DMA mode 2 and below are supported bit 1 1 = Multiword DMA mode 1 and below are supported bit 0 1 = Multiword DMA mode 0 is supported Ultra DMA modes supported bit 15 - 6 0 = Reserved bit 5 1 = Ultra DMA mode 5 and below are supported bit 4 1 = Ultra DMA mode 4 and below are supported bit 3 1 = Ultra DMA mode 3 and below are supported bit 2 1 = Ultra DMA mode 2 and below are supported bit 1 1 = Ultra DMA mode 1 and below are supported bit 0 1 = Ultra DMA mode 0 is supported Maximum LBA Address This is the highest address accepted by the device in the factory default condition. If no DEVICE CONFIGURATION SET command has been executed modifying the factory default condition Command Set / Feature Set Supported bit 15 - 9 0 = Reserved bit 14 0 = Reserved bit 13 0 = Reserved bit 12 1 = SMART selective self-test supported bit 11 1 = Forced Unit Access feature set supported bit 10 0 = Reserved bit 9 0 = Reserved bit 8 1 = 48-bit Addressing feature set supported bit 7 1 = Host Protected Area feature set supported bit 6 0 = Reserved bit 5 0 = Reserved bit 4 0 = Reserved bit 3 1 = Security feature set supported bit 2 1 = SMART error log supported bit 1 1 = SMART self-test supported bit 0 1 = SMART feature set supported Reserved Integrity word bit 15 - 8 Checksum The checksum is the two's complement of the sum of all byte in words 0 through 254 and the byte consisting of bits 7:0 of word 255. Each byte is added with unsigned arithmetic, and overflow is ignored. bit 7 - 0 Signature Code "A5h" Value (HEX.) 0002h 0007h 003Fh 30GB: 037E 3E3Fh 20GB: 0254 297Fh 198Fh 0000h xxA5h K6610170 Rev.2 Dec 22, 2004 - 56 -