Hitachi C4K60 Specifications - Page 51

DMA Data In/Out Command, 3.4. Non-Data Command, 3.5. Command BSY Timing

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7.3.3. DMA Data In/Out Command The Read DMA and Write DMA commands execute data transfer using the slave-DMA channel. The host is required to enable the slave-DMA feature, if using these commands. 1) The host initializes the slave-DMA feature, if using these commands. 2) The host write any required parameters to the Features, Sector Count, LBA Low (Sector Number), LBA Mid (Cylinder low), LBA High (Cylinder High), and Device/Head registers. 3) The host writes the command code to the Command Register. 4) The device sets the DMARQ when it gets ready to transfer. 5) The slave-DMA channel shall respond by negating CS0- and CS1-, asserting DMACK- signal. And it shall begin data transfer using DMA transfer protocol. CS0- and CS1- shall remain negated as long as DMACK- is asserted, and DMARQ and DMACK- signal shall remain asserted until at least one word of data has been transferred. The register contents are not valid during a DMA Data Phase. 6) The device generates the interrupt to the host, when the data transfer has completed. 7) The host resets the slave-DMA channel. 8) The host reads the Status Register. In response to the Status Register being read, the device negates INTRQ. 7.3.4. Non-Data Command Execution of these commands does not involve any data transfer: 1) The host writes any required parameters to the registers. 2) The host writes the command code to the Command Registers. 3) The device sets BSY. 4) When the device has completed processing, it clears BSY and asserts INTRQ. 5) The host reads the Status Register. 6) The device negates INTRQ. 7.3.5. Command BSY Timing The manner in which a command is accepted varies by the three classes of command acceptance all predicated on the fact that to receive a command, BSY=0. The following describes by the conditions under which busy is set after receipt of a command. Class 1 - The device sets busy within 400 ns. Class 2 - The device will set BSY within 400 ns, then sets up the sector buffer for a write operation, then sets DRQ, and clears BSY within 400 ns of setting DRQ. Note: DRQ may be set so quickly on classes 2 that the BSY transition is too short for BSY=1 to be recognized. K6610170 Rev.2 Dec 22, 2004 - 51 -

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K6610170
Rev.2
Dec 22, 2004
- 51 -
7.3.3. DMA Data In/Out Command
The Read DMA and Write DMA commands execute data transfer using the slave-DMA channel.
The host is required to enable the slave-DMA feature, if using these commands.
1)
The host initializes the slave-DMA feature, if using these commands.
2) The host write any required parameters to the Features, Sector Count, LBA Low (Sector Number),
LBA
Mid (Cylinder low), LBA High (Cylinder High), and Device/Head registers.
3)
The host writes the command code to the Command Register.
4)
The device sets the DMARQ when it gets ready to transfer.
5) The slave-DMA channel shall respond by negating CS0- and CS1-, asserting DMACK- signal. And it
shall begin data transfer using DMA transfer protocol.
CS0- and CS1- shall remain negated as long as
DMACK- is asserted, and DMARQ and DMACK- signal shall remain asserted until at least one word of
data has been transferred.
The register contents are not valid during a DMA Data Phase.
6)
The device generates the interrupt to the host, when the data transfer has completed.
7)
The host resets the slave-DMA channel.
8) The host reads the Status Register. In response to the Status Register being read, the device
negates INTRQ.
7.3.4. Non-Data Command
Execution of these commands does not involve any data transfer:
1)
The host writes any required parameters to the registers.
2)
The host writes the command code to the Command Registers.
3)
The device sets BSY.
4)
When the device has completed processing, it clears BSY and asserts INTRQ.
5)
The host reads the Status Register.
6)
The device negates INTRQ.
7.3.5. Command BSY Timing
The manner in which a command is accepted varies by the three classes of command acceptance all
predicated on the fact that to receive a command, BSY=0. The following describes by the conditions
under which busy is set after receipt of a command.
Class 1 - The device sets busy within 400 ns.
Class 2 - The device will set BSY within 400 ns, then sets up the sector buffer for a write operation,
then sets DRQ, and clears BSY within 400 ns of setting DRQ.
Note
: DRQ may be set so quickly on classes 2 that the BSY transition is too short for BSY=1 to be
recognized.