Hitachi C4K60 Specifications - Page 35

Command Register, 1.11. Alternate Status Register, 1.12. Device Control Register

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Page 35 highlights

7.1.10. Command Register The command code is sent to this register. After it is written, execution begins. 7.1.11. Alternate Status Register The information in this register is a duplicate of that in the Status Register. Reading this register will not clear the interrupt. 7.1.12. Device Control Register Bit 7 6 5 4 3 2 1 0 Name HOB - - - - SRST nIEN '0' − HOB (High Order Byte): This bit is defined by 48-bit addressing feature: HOB = 1: The host can read the previous content of the Features, Sector Count, LBA Low, LBA Mid, and LBA High Registers. HOB = 0: The host can read the most recently written content of the above registers. The device clears HOB bit to zero by a write to any command block register. − nIEN(Interrupt Enable): If the device is selected when nIEN is 0, the INTRQ signal is enabled. When nIEN is 1 or when the device is not selected, the INTRQ signal is in a high impedance state. − SRST (Software Reset): When this bit is set, the device is reset. When this bit is cleared, the device exits from the reset state. When two devices are connected through one line in the daisy chain mode, they are reset simultaneously. K6610170 Rev.2 Dec 22, 2004 - 35 -

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K6610170
Rev.2
Dec 22, 2004
- 35 -
7.1.10. Command Register
The command code is sent to this register. After it is written, execution begins.
7.1.11. Alternate Status Register
The information in this register is a duplicate of that in the Status Register.
Reading this register will not clear the interrupt.
7.1.12. Device Control Register
Bit
7
6
5
4
3
2
1
0
Name
HOB
-
-
-
-
SRST
nIEN
'0'
−
HOB (High Order Byte):
This bit is defined by 48-bit addressing feature:
HOB = 1: The host can read the previous content of the Features, Sector Count, LBA Low, LBA
Mid, and LBA High Registers.
HOB = 0: The host can read the most recently written content of the above registers.
The device clears HOB bit to zero by a write to any command block register.
−
nIEN(Interrupt Enable):
If the device is selected when nIEN is 0, the INTRQ signal is enabled. When nIEN is 1 or when the
device is not selected, the INTRQ signal is in a high impedance state.
−
SRST (Software Reset):
When this bit is set, the device is reset. When this bit is cleared, the device exits from the reset
state. When two devices are connected through one line in the daisy chain mode, they are reset
simultaneously.