Hitachi C4K60 Specifications - Page 34

7.1.9. Status Register The current device status is reflected in this register. The contents are updated at the completion of each command. If BSY=1, no other bits in this register are valid. When BSY is cleared, the other bits in this register is valid within 400 ns. If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge, and the pending interrupt is then cleared. Bit 7 6 5 4 3 2 1 Name BSY DRDY DWF DSC DRQ CORR IDX 0 ERR − ERR (Error): This bit indicates that an error occurs during the execution of a command. For more information, refer to the description of the Error register. − IDX (Index): This bit is set once per disk revolution. − CORR (Corrected Data): This bit reports always "1" − DRQ (Data Request): This bit indicates that the device is ready to transfer data between the host and the device. − DSC (Device Seek Complete): This bit indicates that the device head is located on the specified track. If an error has occurred, the value of this bit is not changed until the host reads the Status register. − DFW (Device Write Fault): This bit indicates that an error has occurred during a Write operation. If an error has occurred, the value of this bit is not changed until the host reads the Status register. − DRDY (Device Ready): This bit indicates that the device is ready to respond any command. If an error has occurred, the value of this bit is not changed until the host reads the Status register. This bit is cleared when the power is turned on and then kept cleared until the device gets ready to accept any command. − BSY (Busy): This bit is specified when the device accesses the Command Block Registers. When BSY is 1,the host cannot access the Command Block Registers. If the Command Block Registers are read when BSY is "1", all contents of the Status Register are returned. K6610170 Rev.2 Dec 22, 2004 - 34 -