Hitachi C4K60 Specifications - Page 30

Hitachi C4K60 - Travelstar Slim - Hard Drive Manual

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Table 6.2 Signal List(Continued) Signal name Pin I/O type Description INTRQ 30 O This is an interrupt signal for the host system. This signal is asserted by a selected device when the nIEN bit in the Device Control Register is "0". In other cases, this signal should be a high impedance state. DA0-2 31,33,34 I This is a register address signal from the host system. PDIAG-:CBLID- 32 I/O The host shall wait until the power on or hardware reset sequence *1 is complete for all devices on the cable; CS0- 35 I This device chip selection signal is used to select the Command Block Registers from the host system. CS1- 36 I This device chip selection signal is used to select the Control Block Registers from the host system. DASP- 37 I/O This signal indicates that a device is active when the power is turned on. Upon receipt of a command from the host, the device asserts this signal. At command completion, the device de-asserts this signal. DMARQ 22 O The device shall assert this signal, used for DMA data transfers between host and device, when it is ready to transfer data. DMACK- 29 I The host in response to DMARQ to either acknowledge that data has been accepted, or that data is available shall use this signal. DEVADR 40 I The device is configured as either Device 0 (Master) or Device 1 (Slave) depending upon the signal level of 40 pin DEVADR signal. - When used as Device 0 (Master), DEVADR is open - When used as Device 1 (Slave), the host shall have pull-up resistor. Recommended pull-up resistor is 10K ohm based on +3.3Vcc. *1: PDIAG-:CBLID- (Passed diagnostics: Cable assembly type identifier The DEVADR signal level is as follows. (1) Input signal High level +2.0V to Vcc+0.4V Low level −0.4V to +0.8V The other I/O signal levels are as follows. (1) Input signal High level +2.0V to Vcc+0.5V Low level −0.5V to +0.8V (2) Output signal High level +2.4V to +3.46V or an open circuit Low level +0.4V or less (IOL=2mA), +0.5V or less (IOL=12mA) Note 1) The I/F cable should be no longer than 90mm including the circuit pattern length in the host system. If the cable length is not within this specification, it may cause factional degradations or some errors. K6610170 Rev.2 Dec 22, 2004 - 30 -

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K6610170
Rev.2
Dec 22, 2004
- 30 -
Table 6.2
Signal List(Continued)
Signal name
Pin
I/O type
Description
INTRQ
30
O
This is an interrupt signal for the host system.
This signal is
asserted by a selected device when the nIEN bit in the Device
Control Register is "0". In other cases, this signal should be a high
impedance state.
DA0-2
31,33,34
I
This is a register address signal from the host system.
PDIAG-:CBLID-
*1
32
I/O
The host shall wait until the power on or hardware reset sequence
is complete for all devices on the cable;
CS0-
35
I
This device chip selection signal is used to select the Command
Block Registers from the host system.
CS1-
36
I
This device chip selection signal is used to select the Control Block
Registers from the host system.
DASP-
37
I/O
This signal indicates that a device is active when the power is turned
on.
Upon receipt of a command from the host, the device asserts this
signal. At command completion, the device de-asserts this signal.
DMARQ
22
O
The device shall assert this signal, used for DMA data transfers
between host and device, when it is ready to transfer data.
DMACK-
29
I
The host in response to DMARQ to either acknowledge that data
has been accepted, or that data is available shall use this signal.
DEVADR
40
I
The device is configured as either Device 0 (Master) or Device 1
(Slave) depending upon the signal level of 40 pin DEVADR signal.
- When used as Device 0 (Master),
DEVADR is open
- When used as Device 1 (Slave),
the host shall have pull-up resistor.
Recommended pull-up resistor is 10K ohm based on +3.3Vcc.
*1
: PDIAG-:CBLID- (Passed diagnostics: Cable assembly type identifier
The DEVADR signal level is as follows.
(1) Input signal
High level
+
2.0V
to
Vcc
+
0.4V
Low
level
−
0.4V
to
+
0.8V
The other I/O signal levels are as follows.
(1) Input signal
High level
+
2.0V
to
Vcc
+
0.5V
Low
level
−
0.5V
to
+
0.8V
(2) Output signal
High level
+
2.4V to
+
3.46V or an open circuit
Low
level
+
0.4V or less (IOL=2mA),
+
0.5V or less (IOL=12mA)
Note
1)
The I/F cable should be no longer than 90mm including the circuit pattern length in the host system. If
the cable length is not within this specification, it may cause factional degradations or some errors.