Hitachi C4K60 Specifications - Page 141
Host terminating an Ultra DMA Write
UPC - 683728199449
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DMARQ (device) DMACK(host) STOP (host) DDMARDY(device) Figure 8.12 Host terminating an Ultra DMA Write tLI tMLI tSS tLI tACK tLI tIORDYZ tACK HSTROBE (host) DD(15:0) (host) tCVS CRC tCVH tACK DA0, DA1, DA2, CS0-, CS1- Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode 3(ns) Mode 4(ns) Mode5(ns) Description SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tCVS 70 48 31 20 6.7 10 CRC word valid setup time at sender tCVH 6.2 6.2 6.2 6.2 6.2 10 CRC word valid hold time at sender tLI 0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time tMLI 20 20 20 20 20 20 Interlock time with minimum tAZ 10 10 10 10 10 10 Maximum time allowed for output drivers to release tIORDYZ 20 20 20 20 20 20 Maximum time before releasing IORDY tACK 20 20 20 20 20 20 Setup and hold times for DMACK_ tSS 50 50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of STOP K6610170 Rev.2 Dec 22, 2004 - 141 -