Hitachi C4K60 Specifications - Page 143

Power On and Hardware Reset Timing

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8.3. Power On and Hardware Reset Timing Figure 8.14 Power on and Hardware Reset Timing RESETBSY bit Device 0 (Master) DRDY t PDIAG(out) DASP(out) DASP(in) BSY bit Device 1 (Slave) DRDY PDIAG(out) DASP(out) tM tN0 tR0 tP0 tQ tN1 tR1 tS SYMBOL Description MIN TM RESET- Pulse Width 25 tN0 DRV 0 RESET negation to BSY bit set to one, release PDIAD_ tP0 DRV 0 release DASP-- tR0 DRV 0 sample of DASP- 1 TS DRV 0 sample of PDIAG- 1ms tR1 DRV 1 assert DASP- tN1 DRV 1 negate PDIAG- if asserted TQ DRV 1 assert PDIAG- MAX 400 1 450 31s 400 1 30 Units µs ns ms ms ms ms sec K6610170 Rev.2 Dec 22, 2004 - 143 -

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K6610170
Rev.2
Dec 22, 2004
- 143 -
8.3. Power On and Hardware Reset Timing
Figure 8.14 Power on and Hardware Reset Timing
t
M
t
N0
RESET-
BSY bit
Device 0
t
P0
t
R0
DASP-
DRDY
t
PDIAG-
t
Q
Device 1
BSY bit
t
R1
t
S
DASP-
PDIAG-
DRDY
t
N1
DASP-
(out)
(in)
(out)
(out)
(out)
(Master)
(Slave)
SYMBOL
Description
MIN
MAX
Units
T
M
RESET- Pulse Width
25
ยต
s
t
N0
DRV 0 RESET negation to BSY bit set to one,
release PDIAD_
400
ns
t
P0
DRV 0 release DASP--
1
ms
t
R0
DRV 0 sample of DASP-
1
450
ms
T
S
DRV 0 sample of PDIAG-
1ms
31s
-
t
R1
DRV 1 assert DASP-
400
ms
t
N1
DRV 1 negate PDIAG- if asserted
1
ms
T
Q
DRV 1 assert PDIAG-
30
sec