Hitachi C4K60 Specifications - Page 29
Description of the Interface Signals
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UPC - 683728199449
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6.2.4. Description of the Interface Signals The interface is an ATA(IDE) interface. Reserved pins should be left unconnected. The signal names and the pin numbers are shown in Table 6.1. Table 6.2 shows signal definitions. "I" of I/O type represents an input signal from the device and "O" represents an output signal from the device. Table 6.2 Signal List Signal name Pin RESET- 3 DD0-DD15 5-20 DIOW- 24 STOP *1 DIOR- 25 I/O type I I/O I I HDMARDY*1 HSTROBE *1 IORDY 27 O DDMARDY*1 DSTROBE *1 *1: Signal name in Ultra DMA mode Description This is a reset signal output from the host system and to be used for interface logic circuit. This is a 16-bit bi-directional data bus. The lower 8 bits are used for register access other than data register. The rising edge of this Write Strobe signal clocks data from the host data bus into a register on the device. Assertion of this signal by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst. Activating this Read Strobe signal enables data from a register on the device to be clocked onto the host data bus. The rising edge of this signal latches data at the host. This signal is a flow control signal for Ultra DMA Read. Host asserts this signal, and indicates that the host is ready to receive Ultra DMA Read data . This signal is Write data strobe signal from the host for an Ultra DMA Write. Both the rising and falling edge latch the data from DD(15:0) into the device. This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. This signal is a flow control signal for Ultra DMA Write. Device asserts this signal, and indicates that the device is ready to receive Ultra DMA Write data . This signal is the data in strobe signal from the device for an Ultra DMA Read. Both the rising and falling edge latch the data from DD(15:0) into the host. K6610170 Rev.2 Dec 22, 2004 - 29 -
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