Intel S1200RP Service Guide - Page 84

Memory Configuration

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Server Utilities The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Instruction Cache and Memory Channel use but disabling it may improve performance for some processing loads and on certain benchmarks. Back to [Advanced Screen] - [Screen Map] 27. Direct Cache Access (DCA) Option Values: Enabled Disabled Help Text: Allows processors to increase the I/O performance by placing data from I/O devices directly into the processor cache. Comments: System performance is usually best with Direct Cache Access Enabled. In certain unusual cases, disabling this may give improved results. Back to [Advanced Screen] - [Screen Map] 28. Intel (SMX) Safter Mode Extensions Option Values: Enabled Disabled Help Text: When Enabled, a SMX can utilize the additional hardware Capabilities provided by Safer Mode Extensions. Comments: Back to [Advanced Screen] - [Screen Map] 29. SMM Wait Timeout Option Values: [Entry Field 20 - 3000ms, 20 is default] Help Text: Millisecond timeout waiting for BSP and APs to enter SMM. Range is 20ms to 3000ms. Comments: Amount of time to allow for the SMI Handler to respond to an SMI. If exceeded, BMC generates an SMI Timeout and resets the system. Note: This field is temporary, and will be removed when no longer required. Back to [Advanced Screen] - [Screen Map] Memory Configuration The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that are installed as system memory, and alter BIOS Memory Configuration settings where appropriate. To access this screen from the Main screen, select Advanced > Memory Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen. Intel® Server System P4000RP Family Service Guide 71

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Server Utilities
Intel
®
Server System P4000RP Family Service Guide
71
The next cache line will be prefetched into L1 instruction cache from L2 or system memory during
unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache
line as data.
Comments:
DCU Data Prefetcher is normally
Enabled
, for best efficiency in L1
Instruction
Cache and Memory Channel use but disabling it may improve performance for some
processing loads and on certain benchmarks.
Back to [
Advanced Screen
]
—
[
Screen Map
]
27.
Direct Cache Access (DCA)
Option Values:
Enabled
Disabled
Help Text:
Allows processors to increase the I/O performance by placing data from I/O devices directly into
the processor cache.
Comments:
System performance is usually best with Direct Cache Access Enabled.
In certain unusual cases, disabling this may give improved results.
Back to [
Advanced Screen
]
—
[
Screen Map
]
28.
Intel (SMX) Safter Mode Extensions
Option Values:
Enabled
Disabled
Help Text:
When Enabled, a SMX can utilize the additional hardware
Capabilities provided by Safer Mode
Extensions.
Comments:
Back to [
Advanced Screen
]
—
[
Screen Map
]
29.
SMM Wait Timeout
Option Values:
[Entry Field 20
–
3000ms,
20
is default]
Help Text:
Millisecond timeout waiting for BSP and APs to enter SMM. Range is 20ms to 3000ms.
Comments:
Amount of time to allow for the SMI Handler to respond to an SMI. If
exceeded, BMC generates an SMI Timeout and resets the system.
Note:
This field is temporary, and will be removed when no longer required.
Back to [
Advanced Screen
]
—
[
Screen Map
]
Memory Configuration
The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that are
installed as system memory, and alter BIOS Memory Configuration settings where appropriate.
To access this screen from the
Main
screen, select
Advanced > Memory Configuration
. To move
to another screen, press the <Esc> key to return to the
Advanced
screen, then select the desired
screen.